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CLVC1G175MDBVREP PDF预览

CLVC1G175MDBVREP

更新时间: 2024-11-06 21:03:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
14页 447K
描述
LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6, SOT-23, 6 PIN

CLVC1G175MDBVREP 技术参数

生命周期:Obsolete零件包装代码:SOT-23
包装说明:LSSOP, TSOP6,.11,37针数:6
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.41系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6长度:2.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:150000000 Hz最大I(ol):0.024 A
位数:1功能数量:1
端子数量:6最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:1.45 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:1.6 mm最小 fmax:175 MHz
Base Number Matches:1

CLVC1G175MDBVREP 数据手册

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SN74LVC1G175-EP  
SINGLE D-TYPE FLIP-FLOP  
WITH ASYNCHRONOUS CLEAR  
www.ti.com  
SGLS366AUGUST 2006  
FEATURES  
Controlled Baseline  
– One Assembly Site  
– One Test Site  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– One Fabrication Site  
– 1000-V Charged-Device Model (C101)  
(1)  
Extended Temperature Performance of –55°C  
to 125°C  
Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Enhanced Product-Change Notification  
Qualification Pedigree(1)  
Available in the Texas Instruments  
DBV OR DCK PACKAGE  
(TOP VIEW)  
NanoStar™ and NanoFree™ Packages  
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.3 ns at 3.3 V  
1
2
3
6
5
4
CLK  
GND  
D
CLR  
V
CC  
Q
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Ioff Supports Partial Power-Down-Mode  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
3
2
1
4
5
6
D
GND  
CLK  
Q
V
CC  
CLR  
DESCRIPTION/ORDERING INFORMATION  
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is  
transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low  
state, regardless of the clock edge or data on D.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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