CLOCK
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CLD/CLDP SERIES: CLOCK OSCILLATOR, LVDS, +3.3 VDC or +2.5VDC
DESCRIPTION: A crystal controlled, high frequency, highly stable oscillator, adhering to Low Voltage
Differential Signaling (LVDS) Standards. The output can be Tri-stated to facilitate testing or combined multiple
clocks. The device is contained in a sub-miniature, very low profile, leadless ceramic SMD package with 6 gold
contact pads. This miniature oscillator is ideal for today's automated assembly environments.
APPLICATIONS AND FEATURES:
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Infiniband; 10GbE; Network Processors; SOHO Routing; Switches; WAN Interfaces
Common Frequencies: 106.25 MHz; 125 MHz; 150 MHz; 155.52 MHz; 156.25 MHz; 161.1328 MHz
+3.3 VDC or +2.5VDC LVDS
Frequency Range from 50.000 to 315 MHz
No multiplication
Miniature Ceramic SMD Package Available on Tape and Reel
Lead Free and ROHS Compliant
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ABSOLUTE MAXIMUM RATINGS:
PARAMETER
SYMBOL
VALUE
UNIT
Operating temperature range Ta
-40…+85
-55…+90
°C
Storage temperature range
Supply voltage
T(stg)
°C
Vcc
Vi
-0.5…+5.0
VDC
VDC
VDC
Maximum Input Voltage
Maximum Output Voltage
Vss-0.5…Vcc+0.5
Vss-0.5…Vcc+0.5
Vo
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ELECTRICAL PARAMETERS:
SYMBO
PARAMETER
TEST CONDITIONS*1
VALUE
UNIT
L
Nominal Frequency
Supply Voltage
Supply Current
Output Logic Type
Load
fo
50.000 ~ 315.00**
+3.3 or +2.5 ±5%
80.0 MAX
MHz
VDC
mA
Vcc
Is
LVDS
Connected between Out and Complementary Out
100
Ω
Voh
Vol
Vod
Output logic high
Output logic low
Differential output
Differential output error
Offset Voltage
1.43 Typ, 1.6 Max
0.9 Min, 1.10 Typ
247 Min, 330 Typ, 454 Max
50 Max
1.125 Min, 1.25 Typ, 1.375 Max
50 Max
VDC
VDC
mV
mV
VDC
mV
Output Levels
VOS
OS
Offset error
Duty Cycle
DC
Measured at 50% of Vcc
40/60 to 60/40 or 45/55 to 55/45
%
Rise / Fall Time
tr / tf
Measured at 20/80% and 80/20% Vcc Levels
0.6 TYP *2
ns
ps
Integrated Phase tji RMS, Fj = 12 kHz…20 MHz
Integrated Phase RMS tii offset frequency 50KHz to
80MHz
Deterministic period Jitter tdj using wavecrest analyz. 0.0TYP **
Random period Jitter trj using wavecrest analyz.
0.3 TYP**
0.5 TYP**
ps
Jitter
J
ps
ps
ps
2.5 TYP **
25 TYP**
Peak to Peak Jitter Tp-p using wavecrest analyz.
∆f=10 Hz
£(∆f)
£(∆f)
£(∆f)
£(∆f)
-65
-120
-140
-145
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise typ.
@155.52MHz
∆f=1 KHz
∆f=10 KHz
∆f ≥100 KHz
∆f/fc
±20, ±25, ±50, or ±100 MAX*3
Overall Frequency Stability
Op. Temp., Aging, Load, Supply and Cal. Variations
Ppm
Pin 1
Output Enabled
Output Disabled
En
Dis
High Voltage or No Connect
Ground
0.7•Vcc MIN
0.3•Vcc MAX
VDC
VDC
*1 Test Conditions Unless Stated Otherwise: Nominal Vcc, Nominal Load, +25 ±3°C
*2 Frequency Dependent
*3 Not All Stabilities Available With All Temperature Ranges—Please Consult Factory For Availability
RALTRON ELECTRONICS CORP. ꢀ10651 N.W . 19t h St ꢀMiami, Florida 33172 ꢀU.S.A.
phone: (305) 593-6033 ꢀfax: (305) 594-3973 ꢀe-mail: sales@raltron.com ꢀWEB: http://www.raltron.com