Datasheet > CL3P-67204L-60

CL3P-67204L-60

更新时间： 2024-11-08 08:35:31

品牌	Logo	应用领域
爱特美尔 - ATMEL		先进先出芯片光电二极管
页数	文件大小	规格书
16页	147K
描述
FIFO, 4KX9, 60ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

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CL3P-67204L-60 数据手册

MATRA MHS

L 67203/L 67204

2K × 9 & 4K × 9 / 3.3 Volts CMOS Parallel FIFO

Introduction

The L67203/204 implement a first-in first-out algorithm, Using an array of eigh transistors (8 T) memory cell and

featuring asynchronous read/write operations. The FULL fabricated with the state of the art 1.0 µm lithography

and EMPTY flags prevent data overflow and underflow. named SCMOS, the L 67203/204 combine an extremely

The Expansion logic allows unlimited expansion in word low standby supply current (typ = 1.0 µA) with a fast

size and depth with no timing penalties. Twin address access time at 55 ns over the full temperature range. All

pointers automatically generate internal read and write versions offer battery backup data retention capability

addresses, and no external address information are with a typical power consumption at less than 5 µW.

required for the MHS FIFOs. Address pointers are

For military/space applications that demand superior

automatically incremented with the write pin and read

levels of performance and reliability the L 67203/204 is

pin. The 9 bits wide data are used in data communications

processed according to the methods of the latest revision

applications where a parity bit for error checking is

of the MIL STD 883 (class B or S) and/or ESA SCC 9000.

necessary. The Retransmit pin resets the Read pointer to

zero without affecting the write pointer. This is very

useful for retransmitting data when an error is detected in

the system.

Features

D First-in first-out dual port memory

D Single supply 3.3 ± 0.3 volts

D 2048 × 9 organisation (L 67203)

D 4096 × 9 organisation (L 67204)

D Fast access time

D Fully expandable by word width or depth

D Asynchronous read/write operations

D Empty, full and half flags in single device mode

D Retransmit capability

D Bi-directional applications

Commercial, industrial automotive and military :

55, 60, 65 ns

D Battery back-up operation 2 V data retention

D TTL compatible

D Wide temperature range : – 55 °C to + 125 °C

D High performance SCMOS technology

D 67203L/204L low power

67203V/204V very low power

Rev. C (10/11/94)

12 3 4 5 6 7...16

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与CL3P-67204L-60相关器件

型号	品牌	获取价格	描述	数据表
CL3P-67204L-65	ATMEL	获取价格	FIFO, 4KX9, 65ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CL3P-67204V-60	ATMEL	获取价格	FIFO, 4KX9, 60ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CL3P-67205L-55	TEMIC	获取价格	FIFO, 8KX9, 55ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CL3P-67205V-55	TEMIC	获取价格	FIFO, 8KX9, 55ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CL3P-67205V-60	TEMIC	获取价格	FIFO, 8KX9, 60ns, Asynchronous, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
CL40	ARTESYN	获取价格	Single and triple output
CL-40	AMPHENOL	获取价格	UL Approval (UL 1434 File# E82830)
CL40-7605	ARTESYN	获取价格	Single and triple output
CL40-7605J	ARTESYN	获取价格	Single and triple output
CL40-7608	ARTESYN	获取价格	Single and triple output