Datasheet > CL3256AQC208-10

CL3256AQC208-10

更新时间： 2024-01-03 18:29:07

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
14页	111K
描述
FPGA

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中文翻译

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技术参数
数据手册

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CL3256AQC208-10 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

CL3256AQC208-10 数据手册

CL3256A

Link Processed Logic Device Family

Key Features

u Patented High Fidelity Conversion Technology

u Link Processed Logic Device (LPLD^®) technology offers

the ultimate combination of performance, flexibility, and

low cost

u Functionally, architecturally, and electrically compatible

with industry-standard Altera^®MAX^®3000

u High Density

5,000 Usable gates

256 Macrocells

158 Maximum user I/O pins

u Metal link technology provides very fast, dense

interconnect routing

u Low current consumption

u Supports 3.3 volt operation

u Alpha particle immune

CL3000 P r od u ct F a m ily Over view

Feature

CL3128A

CL3256A

Useable Gates

2,500

5,000

256

Macrocells

128

Logic array Blocks

Max user I/O pins

Speed Grades

158

-4, -5, -7, -10

-5, -6, -7, -10

100-Pin TQFP

144-Pin TQFP

208-Pin PQFP

Packages

3KA tbl 01A

December 2000

Page 121

12 3 4 5 6 7...14

中文翻译

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