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CS2200P-CZZR PDF预览

CS2200P-CZZR

更新时间: 2024-01-06 11:18:43
品牌 Logo 应用领域
凌云 - CIRRUS /
页数 文件大小 规格书
24页 181K
描述
Fractional-N Frequency Synthesizer

CS2200P-CZZR 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP, TSSOP10,.19,20Reach Compliance Code:compliant
风险等级:5.77模拟集成电路 - 其他类型:PHASE LOCKED LOOP
JESD-30 代码:S-PDSO-G10长度:3 mm
功能数量:1端子数量:10
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP10,.19,20封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1.1 mm最大供电电流 (Isup):18 mA
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

CS2200P-CZZR 数据手册

 浏览型号CS2200P-CZZR的Datasheet PDF文件第2页浏览型号CS2200P-CZZR的Datasheet PDF文件第3页浏览型号CS2200P-CZZR的Datasheet PDF文件第4页浏览型号CS2200P-CZZR的Datasheet PDF文件第5页浏览型号CS2200P-CZZR的Datasheet PDF文件第6页浏览型号CS2200P-CZZR的Datasheet PDF文件第7页 
CS2200-OTP  
Fractional-N Frequency Synthesizer  
Features  
General Description  
Delta-Sigma Fractional-N Frequency Synthesis  
The CS2200-OTP is an extremely versatile system  
clocking device that utilizes a programmable phase lock  
loop. The CS2200-OTP is based on an analog PLL ar-  
chitecture comprised of a Delta-Sigma Fractional-N  
Frequency Synthesizer. This architecture allows for fre-  
quency synthesis and clock generation from a stable  
reference clock. The CS2200-OTP has many configura-  
tion options which are set once prior to runtime. At  
runtime there are three hardware configuration pins  
available for mode and feature selection.  
Generates a Low Jitter 6 - 75 MHz Clock  
Relative to 8 - 75 MHz Reference Clock  
Highly Accurate PLL Multiplication Factor  
Maximum Error Less Than 1 PPM  
One-Time Programmability  
Configurable Hardware Control Pins  
Configurable Auxiliary Output  
The CS2200-OTP is available in a 10-pin MSOP pack-  
age in Commercial (-10°C to +70°C) grade. Customer  
development kits are also available for custom device  
prototyping, small production programming, and device  
evaluation. Please see “Ordering Information” on  
page 23 for complete details.  
Flexible Sourcing of Reference Clock  
External Oscillator or Clock Source  
Supports Inexpensive Local Crystal  
Minimal Board Space Required  
No External Analog Loop-filter  
Components  
3.3 V  
Timing Reference  
PLL Output  
Auxiliary  
Output  
Hardware Control  
Hardware Configuration  
PLL Lock Indicator  
8 MHz to 75 MHz  
Low-Jitter Timing  
Reference  
Phase  
Comparator  
Internal  
Loop Filter  
Voltage Controlled  
Oscillator  
6 to 75 MHz  
PLL Output  
Fractional-N  
Divider  
N
Delta-Sigma  
Modulator  
Output to Input  
Clock Ratio  
Copyright Cirrus Logic, Inc. 2009  
AUG '09  
DS842F1  
(All Rights Reserved)  
http://www.cirrus.com  

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