Datasheet > CGS410

CGS410

更新时间： 2024-09-24 22:28:31

品牌	Logo	应用领域
美国国家半导体 - NSC		时钟发生器
页数	文件大小	规格书
18页	287K
描述
Programmable Clock Generator

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数据手册

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CGS410 数据手册

September 1995

CGS410

Programmable Clock Generator

General Description

The CGS410 is a programmable clock generator which pro-

duces a variable frequency clock output for use in graphics,

disk drives and clock synchronizing applications. The

CGS410 produces output clocks in CMOS and differential

formats. The user is able to program the differential output

levels to best suit the levels of the interfacing device. A

common configuration allows PCLK to emulate positive ECL

logic levels, eliminating the need for TTL to ECL translation.

An additional advantage of the CGS410 is its ability to per-

form smooth, glitch-free clock output changes as the user

selects passthru clock sources or changes the VCO

frequency.

A real-time synchronous load clock enable

(LCLK EN) control input allows for the enabling and dis-

abling of the LCLK output. This is suitable for applications

which require the removal of an active LCLK during the

blanking portion of a screen refresh.

The CGS410 is referenced off the XTLIN input which can be

configured for either external crystal or external oscillator

support. All internal frequency generation is referenced from

the XTLIN input. The CGS410 can also be driven by

EXTCLK as desired. EXTCLK may serve as the source from

a fixed clock (for passthru mode), or as an external VCO

input.

On power-up the XTLIN frequency is internally divided by

two and routed to the PCLK outputs, providing a known

power-up output frequency with a 50% duty cycle. The

CGS410 is programmed by a serial stream of data. A serial

bit read can verify the contents of the register.

Features

The CGS410 contains three internal user-selectable low

pass filters (LPFs). A fourth option allows for the use of an

external LPF configuration. Use of the internal filters greatly

simplifies layout, reduces board real estate, and minimizes

part count. A programmable polarity charge pump allows

the user to optimize the optional external LPF circuitry.

Fully programmable frequency generator

Provides frequencies to 135 MHz

Configurable high-speed complementary clock outputs

CMOS output clocks

Glitch-free transitions for clock changes

Powers up in a known state

The primary loop structure of the CGS410 consists of pro-

grammable N and R dividers. Both are contiguous; N can be

any value between 2 and 16383, and R can be any value

between 1 and 1023. Additional dividers of the internal

VCO allow individual programmability for the PCLK,

Single supply ( 5V) operation

Low current draw, ideal for battery applications

Read/write control register

Internal VCO and loop filters

CMOS PCLK, and LCLK outputs.

Connection Diagram

TL/F/11919–1

Important Note: This device is sensitive to noise on certain pins, especially FREQCTL, FILTER, AVDD, and AGND. Special care must be taken with board

layout for optimum performance.

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/11919

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6 7...18

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与CGS410相关器件

型号	品牌	获取价格	描述	数据表
CGS410M	NSC	获取价格	CGS410M
CGS410V	TI	获取价格	135MHz, VIDEO CLOCK GENERATOR, PQCC28, PLASTIC, LCC-28
CGS410VX	TI	获取价格	135MHz, VIDEO CLOCK GENERATOR, PQCC28, PLASTIC, LCC-28
CGS412T250V4L	CDE	获取价格	Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 250V, 50% +Tol, 10% -Tol, 4100
CGS412T250V4L0NG	CDE	获取价格	CAP,AL2O3,4.1MF,250VDC,10% -TOL,50% +TOL
CGS412T250V4L0NL	CDE	获取价格	CAP,AL2O3,4.1MF,250VDC,10% -TOL,50% +TOL
CGS412T250V4L0NN	CDE	获取价格	CAP,AL2O3,4.1MF,250VDC,10% -TOL,50% +TOL
CGS412T250V4L1NG	CDE	获取价格	CAP,AL2O3,4.1MF,250VDC,10% -TOL,50% +TOL
CGS412T250V4L3NG	CDE	获取价格	CAP,AL2O3,4.1MF,250VDC,10% -TOL,50% +TOL
CGS412T250V4L3NL	CDE	获取价格	CAP,AL2O3,4.1MF,250VDC,10% -TOL,50% +TOL

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