TM
CDP1883,
CDP1883C
CMOS 7-Bit Latch
March 1997
and Decoder Memory Interfaces
Features
Description
• Performs Memory Address Latch and Decoder Func-
tions Multiplexed or Non-Multiplexed
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multi-
plexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
• Interfaces Directly with the CDP1800-Series Micropro-
cessors
• Allows Decoding for Systems Up to 32K Bytes
The device is also compatible with non-multiplexed address
Ordering Information
bus microprocessors. By connecting the clock input to V
,
DD
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
TEMP.
RANGE
PKG.
NO.
5V
10V
PACKAGE
o
CDP1883CE CDP1883E
-40 C to
PDIP
E20.3
o
+85 C
The CDP1833 is compatible with CDP1800-series micropro-
cessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operat-
ing voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dual-
in-line plastic packages (E Suffix).
Pinout
CDP1883, CDP1883C
(PDIP)
TOP VIEW
1
2
V
DD
20
19
18
17
16
15
14
13
12
11
CLOCK
MA0
A8
MA1
A9
3
A10
A11
A12
CS0
CS1
MA2
MA3
MA4
MA5
MA6
CE
4
5
6
7
8
9
CS2
CS3
V
10
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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