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CDP1882

更新时间： 2024-02-05 20:07:01
品牌 Logo 应用领域
英特矽尔 - INTERSIL 解码器存储锁存器
页数 文件大小 规格书
8页 51K
描述
CMOS 6-Bit Latch and Decoder Memory Interfaces

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中文翻译

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CDP1882 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP18,.3Reach Compliance Code：unknown
风险等级：5.9JESD-30 代码：R-PDIP-T18
JESD-609代码：e0端子数量：18
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP18,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/10 V
子类别：Other Logic ICs表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

CDP1882 数据手册

 浏览型号CDP1882的Datasheet PDF文件第2页浏览型号CDP1882的Datasheet PDF文件第3页浏览型号CDP1882的Datasheet PDF文件第4页浏览型号CDP1882的Datasheet PDF文件第5页浏览型号CDP1882的Datasheet PDF文件第6页浏览型号CDP1882的Datasheet PDF文件第7页 
CDP1881C,  
CDP1882, CDP1882C  
CMOS 6-Bit Latch  
March 1997  
and Decoder Memory Interfaces  
Features  
Description  
• Performs Memory Address Latch and Decoder  
Functions Multiplexed or Non-Multiplexed  
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit  
memory latch and decoder circuits intended for use in  
CDP1800 series microprocessor systems. They can inter-  
face directly with the multiplexed address bus of this system  
• Decodes Up to 16K Bytes of Memory  
at maximum clock frequency, and up to four 4K x 8-bit mem-  
ories to provide a 16K byte memory system. With four 2K x  
8-bit memories an 8K byte system can be decoded.  
• Interfaces Directly with CDP1800-Series Microproces-  
sors at Maximum Clock Frequency  
• Can Replace CDP1866 and CDP1867 (Upward Speed  
and Function Capability)  
The devices are also compatible with non-multiplexed  
address bus microprocessors. By connecting the clock input  
to VDD, the latches are in the data-following mode and the  
decoded outputs can be used in general purpose memory-  
system applications.  
Ordering Information  
TEMP.  
RANGE  
( C)  
PKG.  
NO.  
The CDP1881C, CDP1882 and CDP1882C are intended for  
use with 2K or 4K byte RAMs and are identical except that in  
the CDP1882 MWR and MRD are excluded.  
o
PACKAGE  
PDIP  
5V  
10V  
CDP1881CE  
CDP1882CE  
CDP1882CEX  
-
-
-
-40 to +85 E20.3  
-40 to +85 E18.3  
-40 to +85 E18.3  
PDIP  
The CDP1882 is functionally identical to the CDP1882C. It  
differs in that the CDP1882 has recommended operating  
voltage range of 4V to 10.5V and the C version has a recom-  
mended operating voltage range of 4V to 6.5V.  
PDIP  
Burn-In  
SBDIP  
-
CDP1882D  
-40 to +85 D18.3  
The CDP1881C, CDP1882 and CDP1882C are supplied in  
20 lead and 18 lead packages, respectively. The  
CDP1881C is supplied only in a dual-in-line plastic pack-  
age (E suffix). The CDP1882 is supplied in dual-in-line,  
hermetic side-brazed ceramic (D suffix) and in plastic (E  
suffix) packages.  
Pinouts  
CDP1881C  
(PDIP)  
TOP VIEW  
CDP1882, CDP1882C  
(PDIP, CERDIP)  
TOP VIEW  
18  
17  
16  
15  
14  
13  
12  
1
CLOCK  
MA5  
MA4  
MA3  
MA2  
MA1  
MA0  
CE  
VDD  
A8  
20  
19  
18  
17  
16  
15  
1
2
3
4
5
6
7
8
9
CLOCK  
VDD  
A8  
MA5  
MA4  
MA3  
MA2  
MA1  
MA0  
MRD  
MWR  
VSS  
2
3
A9  
A9  
4
A10  
A11  
CS0  
A10  
A11  
CS0  
CS1  
5
6
14 CS1  
13 CS2  
7
8
11 CS2  
10 CS3  
9
12  
11  
CS3  
CE  
VSS  
10  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 1367.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19994-1  
12345678

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