Datasheet > CDCV850DGG

CDCV850DGG

更新时间： 2024-11-25 23:41:35

品牌	Logo	应用领域
其他 - ETC		时钟驱动器输出元件
页数	文件大小	规格书
14页	200K
描述
TEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|TSSOP\|48PIN\|PLASTIC

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CDCV850DGG 数据手册

CDCV850

2.5-V PHASE LOCK LOOP CLOCK DRIVER

WITH 2-LINE SERIAL INTERFACE

SCAS647A – OCTOBER 2000 – REVISED NOVEMBER 2000

DGG PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Driver for Double

Data-Rate Synchronous DRAM

Applications

GND

Spread Spectrum Clock Compatible

Operating Frequency: 60 to 140 MHz

Low Jitter (cyc–cyc): ±75 ps

DDQ

Distributes One Differential Clock Input to

Ten Differential Outputs

GND

43 Y6

42 GND

41 GND

40 Y7

Two-Line Serial Interface Provides Output

Enable and Functional Control

Outputs Are Put Into a High-Impedance

State When the Input Differential Clocks

Are <20 MHz

DDQ

SCLK

SDATA

FBIN

48-Pin TSSOP Package

CLK

Consumes <250-µA Quiescent Current

FBIN

External Feedback Pins (FBIN, FBIN) Are

Used to Synchronize the Outputs to the

Input Clocks

DDI

DDQ

FBOUT

GND

AGND

GND

description

The CDCV850 is a high-performance, low-skew,

DDQ

low-jitter zero delay buffer that distributes a

differential clock input pair (CLK, CLK) to ten

differential pairs of clock outputs (Y[0:9], Y[0:9])

and one differential pair of feedback clock outputs

(FBOUT, FBOUT). The clock outputs are con-

GND

trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,

SCLK), and the analog power input (AV ). A two-line serial interface can put the individual output clock pairs

in a high-impedance state. When the AV

purposes.

terminal is tied to GND, the PLL is turned off and bypassed for test

The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation

is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line

serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).

Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to

enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit

is written to the control register. The registers must be accessed in sequential order (i.e., random access of the

registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in

applicationswherethisprogrammingoptionisnotrequired(afterpowerup, alloutputpairswillthenbeenabled).

When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),

the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low

power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.

Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.

This stabilization time is required following power up, as well as changes to various 2-line serial registers that

affect the PLL. The CDCV850 is characterized for operation from 0°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...14

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与CDCV850DGG相关器件

型号	品牌	获取价格	描述	数据表
CDCV850I	TI	获取价格	2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2 LINE SERIAL INTERFACE
CDCV850IDGG	TI	获取价格	2.5-V phase-lock loop differential clock driver with 2-line serial interface 48-TSSOP -40
CDCV850IDGGR	TI	获取价格	2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 t
CDCV850IDGGRG4	TI	获取价格	2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 t
CDCV855	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855I	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855IPW	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855IPWR	TI	获取价格	暂无描述
CDCV855PW	TI	获取价格	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCV855PWR	TI	获取价格	1:4 DDR PLL clock driver 28-TSSOP 0 to 70

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