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ꢈ ꢉꢄ ꢊꢂ ꢋꢌꢍ ꢎꢏ ꢐ ꢑꢀ ꢒ ꢐ ꢑ ꢑꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢇ ꢂ ꢏꢓ
ꢔ ꢇꢕ ꢌ ꢈ ꢊꢐ ꢇꢖꢏ ꢎꢏ ꢓꢇꢍ ꢐ ꢇꢖ ꢕꢏ ꢓꢗꢍ ꢀꢏ
SCAS647B − OCTOBER 2000 − REVISED DECEMBER 2002
DGG PACKAGE
(TOP VIEW)
D
Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
GND
Y0
GND
Y5
1
48
47
46
45
44
D
D
D
D
D
D
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 140 MHz
Low Jitter (cyc−cyc): 75 ps
2
Y0
Y5
3
V
V
4
DDQ
Y1
DDQ
Y6
5
Distributes One Differential Clock Input to
Ten Differential Outputs
Y1
GND
GND
Y2
6
43 Y6
7
42 GND
41 GND
40 Y7
Two-Line Serial Interface Provides Output
Enable and Functional Control
8
9
Outputs Are Put Into a High-Impedance
State When the Input Differential Clocks
Are <20 MHz
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Y2
Y7
V
V
DDQ
DDQ
SCLK
SDATA
FBIN
D
D
D
48-Pin TSSOP Package
CLK
CLK
Consumes <250-µA Quiescent Current
FBIN
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
V
V
DDI
DDQ
AV
FBOUT
FBOUT
GND
Y8
DD
AGND
GND
Y3
description
Y3
Y8
The CDCV850 is a high-performance, low-skew,
V
V
DDQ
Y4
DDQ
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are con-
Y9
Y4
Y9
GND
GND
trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,
SCLK), and the analog power input (AV ). A two-line serial interface can put the individual output clock pairs
DD
in a high-impedance state. When the AV
purposes.
terminal is tied to GND, the PLL is turned off and bypassed for test
DD
The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line
serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).
Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to
enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit
is written to the control register. The registers must be accessed in sequential order (i.e., random access of the
registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in
applications where this programming option is not required (after power up, all output pairs will then be enabled).
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),
the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low
power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as changes to various 2-line serial registers that
affect the PLL. The CDCV850 is characterized for both commercial and industrial temperature ranges.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated
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1
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