Datasheet > CDCF2509_15

CDCF2509_15

更新时间： 2024-11-17 02:58:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
11页	141K
描述
3.3V Phase-Lock Loop Clock Driver

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CDCF2509_15 数据手册

CDCF2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS624A – APRIL 1999 REVISED MAY 1999

PW PACKAGE

(TOP VIEW)

Designed to Meet PC133 SDRAM

Registered DIMM Specification Rev. 0.9

Spread Spectrum Clock Compatible

AGND

CLK

Operating Frequency 25 MHz to 140 MHz

Static tPhase Error Distribution at 66MHz to

133 MHz is ±125 ps

1Y0

1Y1

1Y2

GND

1Y3

2Y0

2Y1

GND

2Y2

2Y3

Jitter (cyc – cyc) at 66 MHz to 133 MHz is

|70| ps

Available in Plastic 24-Pin TSSOP

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

1Y4

Distributes One Clock Input to One Bank of

Five and One Bank of Four Outputs

FBOUT

FBIN

Separate Output Enable for Each Output

Bank

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

description

The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled

or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in

phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDCF2509 is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

中文翻译

下载PDF

与CDCF2509_15相关器件

型号	品牌	获取价格	描述	数据表
CDCF2509_17	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF2509PW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF2509PWG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 70
CDCF2509PWLE	TI	获取价格	CDCF SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, PLAST
CDCF2509PWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF2509PWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 70
CDCF2510	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF2510PW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCF2510PWLE	TI	获取价格	CDCF SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, PLAS
CDCF2510PWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDCF2509_15相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

14
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

8
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

36
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCF2509_15

CDCF2509_15 数据手册

与CDCF2509_15相关器件

与CDCF2509_15相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCF2509_15

CDCF2509_15 数据手册

与CDCF2509_15相关器件

与CDCF2509_15相关文章

您还可以找

您在本页遇到什么问题？