5秒后页面跳转
CDC391DR PDF预览

CDC391DR

更新时间: 2024-09-25 19:04:07
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
7页 118K
描述
1-To-6 Clock Driver With Selectable Polarity 16-SOIC

CDC391DR 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.48JESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.048 A
湿度敏感等级:1位数:1
功能数量:1端口数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:5 ns传播延迟(tpd):5 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Drivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

CDC391DR 数据手册

 浏览型号CDC391DR的Datasheet PDF文件第2页浏览型号CDC391DR的Datasheet PDF文件第3页浏览型号CDC391DR的Datasheet PDF文件第4页浏览型号CDC391DR的Datasheet PDF文件第5页浏览型号CDC391DR的Datasheet PDF文件第6页浏览型号CDC391DR的Datasheet PDF文件第7页 
ꢀ ꢁꢀ ꢂꢃ ꢄ  
ꢄ ꢅꢆ ꢇꢈꢉ ꢊ ꢋ ꢌ ꢅꢆ ꢇꢈꢉ ꢀꢆ ꢋ ꢀꢍ ꢁ ꢎꢇ ꢏ ꢉꢎ  
ꢐ ꢇꢊ ꢑ ꢒꢉ ꢆꢉ ꢀꢊꢓꢔꢆ ꢉ ꢕꢋ ꢆ ꢓꢎꢇ ꢊꢖ ꢓꢈꢁ ꢂ ꢅꢒꢊꢓꢊ ꢉ ꢋ ꢗꢊ ꢕ ꢗꢊꢒ  
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995  
D PACKAGE  
(TOP VIEW)  
D Low Output Skew for Clock-Distribution  
and Clock-Generation Applications  
D TTL-Compatible Inputs and Outputs  
1Y1  
1T/C  
GND  
1Y2  
1Y3  
GND  
2Y1  
2Y2  
GND  
3Y1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
D Distributes One Clock Input to Six Clock  
Outputs  
V
CC  
D Polarity Control Selects True or  
2T/C  
A
Complementary Outputs  
V
D Distributed V  
and GND Pins Reduce  
CC  
CC  
Switching Noise  
3T/C  
OE  
D High-Drive Outputs (48-mA I  
,
OH  
48-mA I  
)
OL  
D State-of-the-Art EPIC-ΙΙBBiCMOS Design  
Significantly Reduces Power Dissipation  
D Packaged in Plastic Small-Outline Package  
description  
The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew  
for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and  
complementary outputs can be obtained. The output-enable (OE) input is provided to disable the outputs to a  
high-impedance state.  
The CDC391 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
Z
L
OE  
H
L
T/C  
X
A
X
L
L
L
L
H
L
H
H
L
L
H
L
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
ꢊꢣ  
Copyright 1995, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢡꢣ  
ꢞꢜ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

CDC391DR 替代型号

型号 品牌 替代类型 描述 数据表
CDC391D TI

完全替代

1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS

与CDC391DR相关器件

型号 品牌 获取价格 描述 数据表
CDC391DRG4 TI

获取价格

1-To-6 Clock Driver With Selectable Polarity 16-SOIC
CDC392 TI

获取价格

1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
CDC392D TI

获取价格

1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
CDC392DBLE TI

获取价格

暂无描述
CDC392DR TI

获取价格

1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
CDC3RL02 TI

获取价格

LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER
CDC3RL02_16 TI

获取价格

Low Phase-Noise Two-Channel Clock Fan-Out Buffer
CDC3RL02BYFPR TI

获取价格

暂无描述
CDC3RL02YFPR TI

获取价格

LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER
CDC3S04 TI

获取价格

Quad Sine-Wave Clock Buffer With LDO