5秒后页面跳转
捷配首页

Datasheet > 信号电路 > 锁相环或频率合成电路> CD74HCT7046AEE4
CD74HCT7046AEE4 PDF预览

CD74HCT7046AEE4

更新时间： 2024-09-08 22:34:03
品牌 Logo 应用领域
德州仪器 - TI 信号电路锁相环或频率合成电路光电二极管
页数 文件大小 规格书
26页 301K
描述
Phase-Locked Loop with VCO and Lock Detector

阅读下载

中文翻译

获取价格

CD74HCT7046AEE4 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.45
Is Samacsys：N模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：R-PDIP-T16JESD-609代码：e4
长度：19.3 mm功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：3.9 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.35 mmBase Number Matches：1

CD74HCT7046AEE4 数据手册

 浏览型号CD74HCT7046AEE4的Datasheet PDF文件第2页浏览型号CD74HCT7046AEE4的Datasheet PDF文件第3页浏览型号CD74HCT7046AEE4的Datasheet PDF文件第4页浏览型号CD74HCT7046AEE4的Datasheet PDF文件第5页浏览型号CD74HCT7046AEE4的Datasheet PDF文件第6页浏览型号CD74HCT7046AEE4的Datasheet PDF文件第7页 
CD74HC7046A,  
CD74HCT7046A  
Data sheet acquired from Harris Semiconductor  
SCHS218C  
Phase-Locked Loop  
with VCO and Lock Detector  
February 1998 - Revised October 2003  
Features  
Description  
• Center Frequency of 18MHz (Typ) at V  
Minimum Center Frequency of 12MHz at V  
= 5V,  
The CD74HC7046A and CD74HCT7046A high-speed  
silicon-gate CMOS devices, specified in compliance with  
JEDEC Standard No. 7A, are phase-locked-loop (PLL)  
circuits that contain a linear voltage-controlled oscillator  
(VCO), two-phase comparators (PC1, PC2), and a lock  
detector. A signal input and a comparator input are common  
to each comparator. The lock detector gives a HIGH level at  
pin 1 (LD) when the PLL is locked. The lock detector  
CC  
CC = 4.5V  
[ /Title  
(CD74  
HC704  
6A,  
CD74  
HCT70  
46A)  
• Choice of Two Phase Comparators  
- Exclusive-OR  
- Edge-Triggered JK Flip-Flop  
• Excellent VCO Frequency Linearity  
• VCO-Inhibit Control for ON/OFF Keying and for Low  
Standby Power Consumption  
capacitor must be connected between pin 15 (C ) and pin  
LD  
8 (Gnd). For a frequency range of 100kHz to 10MHz, the  
lock detector capacitor should be 1000pF to 10pF,  
respectively.  
• Minimal Frequency Drift  
/Sub-  
• Zero Voltage Offset Due to Op-Amp Buffer  
ject  
The signal input can be directly coupled to large voltage  
signals, or indirectly coupled (with a series capacitor) to  
small voltage signals. A self-bias input circuit keeps small  
voltage signals within the linear region of the input amplifiers.  
With a passive low-pass filter, the 7046A forms a second-  
order loop PLL. The excellent VCO linearity is achieved by  
the use of linear op-amp techniques.  
• Operating Power-Supply Voltage Range  
(Phase-  
Locked  
Loop  
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V  
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
PART NUMBER  
CD74HC7046AE  
( C)  
PACKAGE  
16 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
CD74HC7046AM  
CD74HC7046AMT  
CD74HC7046AM96  
CD74HCT7046AE  
CD74HCT7046AM  
CD74HCT7046AMT  
CD74HCT7046AM96  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
Applications  
• FM Modulation and Demodulation  
• Frequency Synthesis and Multiplication  
• Frequency Discrimination  
• Tone Decoding  
• Data Synchronization and Conditioning  
• Voltage-to-Frequency Conversion  
• Motor-Speed Control  
• Related Literature  
- AN8823, CMOS Phase-Locked-Loop Application  
Using the CD74HC/HCT7046A and  
CD74HC/HCT7046A  
0.1  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
1234567...26

中文翻译

下载PDF

CD74HCT7046AEE4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT7046AE TI

类似代替

 Phase-Locked Loop with VCO and Lock Detector

与CD74HCT7046AEE4相关器件

型号 品牌 获取价格 描述 数据表
CD74HCT7046AEN ETC

获取价格

 		Analog IC
CD74HCT7046AEX RENESAS

获取价格

 		CD74HCT7046AEX
CD74HCT7046AF ETC

获取价格

 		Analog IC
CD74HCT7046AH ETC

获取价格

 		Analog Phase-Locked Loop
CD74HCT7046AM TI

获取价格

 		Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AM96 TI

获取价格

 		Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AM96E4 TI

获取价格

 		Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AM96G4 TI

获取价格

 		Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AME4 TI

获取价格

 		Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AMG4 TI

获取价格

 		Phase-Locked Loop with VCO and Lock Detector

与CD74HCT7046AEE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证