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CD74HCT640E

更新时间： 2024-01-27 18:50:58
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
11页 268K
描述
High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting

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中文翻译

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CD74HCT640E 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：SOP, SOP20,.4Reach Compliance Code：unknown
风险等级：5.92控制类型：COMMON CONTROL
计数方向：BIDIRECTIONALJESD-30 代码：R-PDSO-G20
JESD-609代码：e0最大I（ol）：0.006 A
位数：8功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：5 VProp。Delay @ Nom-Sup：28 ns
子类别：Bus Driver/Transceivers标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

CD74HCT640E 数据手册

 浏览型号CD74HCT640E的Datasheet PDF文件第2页浏览型号CD74HCT640E的Datasheet PDF文件第3页浏览型号CD74HCT640E的Datasheet PDF文件第4页浏览型号CD74HCT640E的Datasheet PDF文件第5页浏览型号CD74HCT640E的Datasheet PDF文件第6页浏览型号CD74HCT640E的Datasheet PDF文件第7页 
CD54HC640, CD74HC640,  
CD54HCT640, CD74HCT640  
Data sheet acquired from Harris Semiconductor  
SCHS192B  
High-Speed CMOS Logic  
Octal Three-State Bus Transceiver, Inverting  
January 1998 - Revised May 2003  
Features  
Description  
• Buffered Inputs  
The ’HC640 and ’HCT640 silicon-gate CMOS three-state  
bidirectional inverting and non-inverting buffers are intended  
for two-way asynchronous communication between data  
buses. They have high drive current outputs which enable  
high-speed operation when driving large bus capacitances.  
These circuits possess the low power dissipation of CMOS  
• Three-State Outputs  
[ /Title  
(CD74  
HC640  
,
• Applications in Multiple-Data-Bus Architecture  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
circuits, and have speeds comparable to low power Schottky  
CD74  
HCT64  
0)  
/Sub-  
ject  
(High  
Speed  
CMOS  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TTL circuits. They can drive 15 LSTTL loads. The ’HC640  
and ’HCT640 are inverting buffers.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
The direction of data flow (A to B, B to A) is controlled by the  
DIR input.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Outputs are enabled by a low on the Output Enable input  
(OE); a high OE puts these devices in the high impedance  
mode.  
• HC Types  
- 2V to 6V Operation  
Ordering Information  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
TEMP. RANGE  
o
PART NUMBER  
CD54HC640F3A  
CD54HCT640F3A  
CD74HC640E  
( C)  
PACKAGE  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld PDIP  
• HCT Types  
- 4.5V to 5.5V Operation  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
CD74HC640M  
20 Ld SOIC  
Pinout  
CD74HCT640E  
CD74HCT640M  
20 Ld PDIP  
CD54HC640, CD54HCT640  
(CERDIP)  
20 Ld SOIC  
CD74HC640, CD74HCT640  
(PDIP, SOIC)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
V
DIR  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
20  
19  
CC  
OE  
18 B0  
17 B1  
16 B2  
15 B3  
14 B4  
13 B5  
12  
B6  
GND 10  
11 B7  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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中文翻译

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CD74HCT640E 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT640M TI

完全替代

 High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting
5962-8974001RA TI

完全替代

 High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting
CD54HCT640F3A TI

完全替代

 High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting

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