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CD74HCT640 PDF预览

CD74HCT640

更新时间: 2024-02-07 07:17:27
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
8页 40K
描述
High Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting

CD74HCT640 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP20,.4Reach Compliance Code:unknown
风险等级:5.92控制类型:COMMON CONTROL
计数方向:BIDIRECTIONALJESD-30 代码:R-PDSO-G20
JESD-609代码:e0最大I(ol):0.006 A
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 VProp。Delay @ Nom-Sup:28 ns
子类别:Bus Driver/Transceivers标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

CD74HCT640 数据手册

 浏览型号CD74HCT640的Datasheet PDF文件第2页浏览型号CD74HCT640的Datasheet PDF文件第3页浏览型号CD74HCT640的Datasheet PDF文件第4页浏览型号CD74HCT640的Datasheet PDF文件第5页浏览型号CD74HCT640的Datasheet PDF文件第6页浏览型号CD74HCT640的Datasheet PDF文件第7页 
CD74HC640,  
CD74HCT640  
Data sheet acquired from Harris Semiconductor  
SCHS192  
High Speed CMOS Logic  
Octal Three-State Bus Transceiver, Inverting  
January 1998  
(PDIP, SOIC)  
TOP VIEW  
Features  
• Buffered Inputs  
• Three-State Outputs  
[ /Title  
(CD74  
HC640  
,
CD74  
HCT64  
0)  
/Sub-  
ject  
(High  
Speed  
CMOS  
1
2
3
4
5
6
7
8
9
V
DIR  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
20  
19  
CC  
• Applications in Multiple-Data-Bus Architecture  
OE  
• Fanout (Over Temperature Range)  
18 B0  
17 B1  
16 B2  
15 B3  
14 B4  
13 B5  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
12  
B6  
GND 10  
11 B7  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
Description  
• HCT Types  
The Harris CD74HC640 and CD74HCT640 silicon-gate  
CMOS three-state bidirectional inverting and non-inverting  
buffers are intended for two-way asynchronous  
communication between data buses. They have high drive  
current outputs which enable high-speed operation when  
driving large bus capacitances. These circuits possess the  
low power dissipation of CMOS circuits, and have speeds  
comparable to low power Sckottky TTL circuits. They can  
drive 15 LSTTL loads. The CD74HC640 and CD74HCT640  
are inverting buffers.  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
Pinout  
CD74HC640, CD74HCT640  
Functional Diagram  
A0  
B0  
A1  
THRU  
A6  
B1  
THRU  
B6  
A7  
B7  
OE  
OUTPUT ENABLE AND  
V
= 20  
CC  
GND = 10  
DIRECTION-SELECT LOGIC  
DIR  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1677.1  
Copyright © Harris Corporation 1998  
1

CD74HCT640 替代型号

型号 品牌 替代类型 描述 数据表
CD54HCT640 TI

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