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CD74HCT20M PDF预览

CD74HCT20M

更新时间: 2024-11-23 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 47K
描述
High Speed CMOS Logic Dual 4-Input NAND Gate

CD74HCT20M 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.95Is Samacsys:N
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:2输入次数:4
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:42 ns传播延迟(tpd):42 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gate
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

CD74HCT20M 数据手册

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CD74HC20,  
CD74HCT20  
Data sheet acquired from Harris Semiconductor  
SCHS130  
High Speed CMOS Logic  
Dual 4-Input NAND Gate  
August 1997  
Features  
Description  
• Buffered Inputs  
The Harris CD74HC20, CD74HCT20, logic gates utilize  
silicon gate CMOS technology to achieve operating speeds  
similar to LSTTL gates with the low power consumption of  
standard CMOS integrated circuits. All devices have the  
ability to drive 10 LSTTL loads. The 74HCT logic family is  
functionally pin compatible with the standard 74LS logic  
family.  
• Typical Propagation Delay: 8ns at V  
o
= 5V,  
[ /Title  
(CD74H  
C20,  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
CD74H  
CT20)  
/Subject  
(High  
Speed  
CMOS  
Logic  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC20E  
CD74HCT20E  
CD74HC20M  
CD74HCT20M  
CD54HC20W  
NOTES:  
( C)  
PACKAGE  
14 Ld PDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
Wafer  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
E14.3  
• HC Types  
E14.3  
Dual 4-  
Input  
- 2V to 6V Operation  
M14.15  
M14.15  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
2. Die for this part number is available which meets all electrical  
specifications. Please contact your local sales office or Harris  
customer service for ordering information.  
Pinout  
CD74HC20, CD74HCT20  
(PDIP, SOIC)  
TOP VIEW  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
13 2D  
12 2C  
11 NC  
10 2B  
NC  
1C  
1D  
1Y  
9
8
2A  
2Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1601.1  
Copyright © Harris Corporation 1997  
1

CD74HCT20M 替代型号

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