CD74HCT137

更新时间： 2024-11-18 23:04:31

品牌	Logo	应用领域
德州仪器 - TI		解复用器锁存器
页数	文件大小	规格书
10页	67K
描述
High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

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数据手册

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CD74HCT137 数据手册

CD74HC137, CD74HCT137,

CD74HC237, CD74HCT237

Data sheet acquired from Harris Semiconductor

SCHS146

High Speed CMOS Logic, 3-to-8 Line Decoder

Demultiplexer with Address Latches

March 1998

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

[ /Title

(CD74

HC137

- Active High for CD74HC237 and CD74HCT237

• l/O Port or Memory Selector

• Two Enable Inputs to Simplify Cascading

CD74

HCT13

• Typical Propagation Delay of 13ns at V

= 5V,

15pF, T = 25 C (CD74HC237)

• Fanout (Over Temperature Range)

CD74

HC237

CD74

HCT23

/Sub-

ject

(High

Speed

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30%, of V

IL IH

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

(PDIP, SOIC)

TOP VIEW

16 V

15 Y

14 Y

13 Y

12 Y

11 Y

10 Y

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1886.1

12 3 4 5 6 7...10

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