CD74HCT107

更新时间： 2024-11-25 23:00:43

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
8页	59K
描述
Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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中文翻译

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数据手册

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CD74HCT107 数据手册

CD74HC107,

CD74HCT107

Data sheet acquired from Harris Semiconductor

SCHS139

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

March 1998

Features

Description

• Hysteresis on Clock Inputs for Improved Noise Immu-

nity and Increased Input Rise and Fall Times

The Harris CD74HC107 and CD74HCT107 utilize silicon

gate CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits, together

with the ability to drive 10 LSTTL loads.

[ /Title

(CD74

HC107

CD74

HCT10

/Sub-

ject

(Dual

J-K

Flip-

Flop

with

Reset

Nega-

tive-

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Reset and Clock

inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Reset is

accomplished asynchronously by a low level input.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

• Fanout (Over Temperature Range)

This device is functionally identical to the HC/HCT73 but

differs in terminal assignment and in some parametric limits.

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

The 74HCT logic family is functionally as well as pin

• Wide Operating Temperature Range . . . -55 C to 125 C compatible with the standard 74LS family.

• Balanced Propagation Delay and Transition Times

Ordering Information

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

TEMP. RANGE

PKG.

NO.

PART NUMBER

CD74HC107E

CD74HCT107E

CD74HC107M

NOTES:

( C)

PACKAGE

14 Ld PDIP

14 Ld SOIC

• HC Types

-55 to 125

E14.3

- 2V to 6V Operation

E14.3

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

M14.15

at V

= 5V

• HCT Types

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

2. Wafer and die is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

CD74HC107, CD74HCT107

(PDIP, SOIC)

TOP VIEW

14 V

13 1R

12 1CP

11 2K

10 2R

2CP

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1722.1

12 3 4 5 6 7 8

中文翻译

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与CD74HCT107相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT107E	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT107EE4	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT107EN	ETC	获取价格	Logic IC
CD74HCT107EX	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,DIP,14PIN,PLASTIC
CD74HCT107F	ETC	获取价格	Logic IC
CD74HCT107H	ETC	获取价格	J-K-Type Flip-Flop
CD74HCT107M	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,SOP,14PIN,PLASTIC
CD74HCT107M	ROCHESTER	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
CD74HCT107M96	RENESAS	获取价格	J-K Flip-Flop, HCT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C
CD74HCT109	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

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