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CD74HCT02 PDF预览

CD74HCT02

更新时间: 2024-11-22 23:00:39
品牌 Logo 应用领域
德州仪器 - TI
页数 文件大小 规格书
6页 41K
描述
High Speed CMOS Logic Quad Two-Input NOR Gate

CD74HCT02 数据手册

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CD74HC02,  
CD74HCT02  
Data sheet acquired from Harris Semiconductor  
SCHS125  
High Speed CMOS Logic  
Quad Two-Input NOR Gate  
March 1998  
at V  
= 5V  
Features  
CC  
• HCT Types  
• Buffered Inputs  
- 4.5V to 5.5V Operation  
• Typical Propagation Delay: 7ns at V  
o
= 5V,  
[ /Title  
(CD74H  
C02,  
CD74H  
CT02)  
/Subject  
(High  
Speed  
CMOS  
Logic  
CC  
- Direct LSTTL Input Logic Compatibility,  
C = 15pF, T = 25 C  
L
A
V = 0.8V (Max), V = 2V (Min)  
IL IH  
• Fanout (Over Temperature Range)  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
• Related Literature  
- CD54HC02F3A and CD54HCT02F3A Military  
Data Sheet, Document Number 3754  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Description  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The Harris CD74HC02, CH74HCT02 logic gates utilize  
silicon-gate CMOS technology to achieve operating speeds  
similar to LSTTL gates with the low power consumption of  
standard CMOS integrated circuits. All devices have the ability  
to drive 10 LSTTL loads. The 74HCT logic family is  
• HC Types  
Quad  
Two-  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
Pinout  
CD74HC02, CD74HCT02  
(PDIP, SOIC)  
TOP VIEW  
1Y  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 4Y  
12 4B  
11 4A  
10 3Y  
1B  
2Y  
2A  
2B  
9
8
3B  
3A  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1647.1  
Copyright © Harris Corporation 1998  
1

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