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CD74HCT00M96 PDF预览

CD74HCT00M96

更新时间: 2024-11-22 23:00:39
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 265K
描述
High Speed CMOS Logic Quad 2-Input NAND Gate

CD74HCT00M96 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.7Is Samacsys:N
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):30 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

CD74HCT00M96 数据手册

 浏览型号CD74HCT00M96的Datasheet PDF文件第2页浏览型号CD74HCT00M96的Datasheet PDF文件第3页浏览型号CD74HCT00M96的Datasheet PDF文件第4页浏览型号CD74HCT00M96的Datasheet PDF文件第5页浏览型号CD74HCT00M96的Datasheet PDF文件第6页浏览型号CD74HCT00M96的Datasheet PDF文件第7页 
CD54HC00, CD74HC00,  
CD54HCT00, CD74HCT00  
Data sheet acquired from Harris Semiconductor  
SCHS116C  
High-Speed CMOS Logic  
Quad 2-Input NAND Gate  
January 1998 - Revised September 2003  
Features  
Description  
• Buffered Inputs  
The  
CD54HC00,  
CD74HC00,  
CD54HCT00,  
and  
CD74HCT00 logic gates utilize silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The 74HCT logic family is functionally pin  
compatible with the standard 74LS logic family.  
• Typical Propagation Delay: 7ns at V  
o
= 5V,  
[ /Title  
(CD54  
HC00,  
CD54  
HCT00  
,
CD74  
HC00,  
CD74  
HCT00  
)
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
Ordering Information  
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC00F3A  
CD54HCT00F3A  
CD74HC00E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Alternate Source is Philips/Signetics  
• HC Types  
/Sub-  
- 2V to 6V Operation  
CD74HC00M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC00MT  
CD74HC00M96  
CD74HCT00E  
CD74HCT00M  
CD74HCT00MT  
CD74HCT00M96  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
Pinout  
CD54HC00, CD54HCT00,  
(CERDIP)  
CD74HC00, CD74HCT00  
(PDIP, SOIC)  
TOP VIEW  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
13 4B  
12 4A  
11 4Y  
10 3B  
1Y  
2A  
2B  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD74HCT00M96 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC00M TI

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High Speed CMOS Logic Quad 2-Input NAND Gate
SN74HC00DR TI

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QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN74HC00D TI

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QUADRUPLE 2-INPUT POSITIVE-NAND GATES

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