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CD74HC646ME4 PDF预览

CD74HC646ME4

更新时间: 2024-11-08 19:41:19
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 321K
描述
Registered Bus Transceiver, HC/UH Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, PLASTIC, SOIC-24

CD74HC646ME4 技术参数

生命周期:Contact Manufacturer包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65其他特性:WITH DIRECTION CONTROL
系列:HC/UHJESD-30 代码:R-PDSO-G24
长度:15.4 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):205 ns座面最大高度:2.65 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

CD74HC646ME4 数据手册

 浏览型号CD74HC646ME4的Datasheet PDF文件第2页浏览型号CD74HC646ME4的Datasheet PDF文件第3页浏览型号CD74HC646ME4的Datasheet PDF文件第4页浏览型号CD74HC646ME4的Datasheet PDF文件第5页浏览型号CD74HC646ME4的Datasheet PDF文件第6页浏览型号CD74HC646ME4的Datasheet PDF文件第7页 
CD74HC646  
Data sheet acquired from Harris Semiconductor  
SCHS193A  
High-Speed CMOS Logic  
Octal Bus Transceiver/Register, Three-State  
January 1998 - Revised May 2003  
Features  
Description  
• Independent Registers for A and B Buses  
• Non-Inverting  
The CD74HC646 is an octal bus transceiver/register with  
three-state non-inverting outputs. This device is a bus  
transceiver with D-type flip-flops which act as internal storage  
registers. Data on the A bus or the B bus can be clocked into  
the registers on the Low-to-High transition of either CAB or  
CBA clock inputs. Outputs enable (OE) and direction (DIR)  
inputs control the transceiver functions. Data present at the  
high impedance output can be stored in either register or both  
but only one of the two buses can be enabled as outputs at  
any one time. The select controls (SAB and SBA) can  
multiplex stored and transparent (real time) data. The  
direction control determines which data bus will receive data  
when the output enable (OE) is Low. In the high impedance  
mode (output enable High), A data can be stored in one  
register and B data can be stored in the other register. The  
clocks are not gated with the direction (DIR) and output  
enable (OE) terminals; data at the A or B terminals can be  
clocked into the storage flip-flops at any time.  
• Three-State Outputs  
• Drives 15 LSTTL Loads  
• Typical Propagation Delay = 12ns (A to B, B to A) at  
o
V
= 5V, C = 15pF, T = 25 C  
CC  
L A  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
Ordering Information  
- High Noise Immunity: N = 30%, N = 30% of V  
IL  
IH  
CC  
at V  
= 5V  
TEMP.  
o
CC  
PART NUMBER  
CD74HC646M  
RANGE ( C)  
-55 to 125  
-55 to 125  
PACKAGE  
24 Ld SOIC  
24 Ld SOIC  
Pinout  
CD74HC646M96  
CD74HC646  
(SOIC)  
TOP VIEW  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel.  
CAB  
1
2
3
4
5
6
7
8
9
24  
V
CC  
SAB  
DIR  
A0  
23 CBA  
22 SBA  
21 OE  
20 B0  
19 B1  
18 B2  
17 B3  
16 B4  
15 B5  
14 B6  
13 B7  
A1  
A2  
A3  
A4  
A5  
A6 10  
A7 11  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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