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CD74HC640M96 PDF预览

CD74HC640M96

更新时间： 2024-09-23 19:18:23
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
13页 278K
描述
HC/UH SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO20

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CD74HC640M96 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknown风险等级：5.6
其他特性：WITH DIRECTION CONTROL系列：HC/UH
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：135 ns
认证状态：Not Qualified座面最大高度：2.65 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

CD74HC640M96 数据手册

 浏览型号CD74HC640M96的Datasheet PDF文件第2页浏览型号CD74HC640M96的Datasheet PDF文件第3页浏览型号CD74HC640M96的Datasheet PDF文件第4页浏览型号CD74HC640M96的Datasheet PDF文件第5页浏览型号CD74HC640M96的Datasheet PDF文件第6页浏览型号CD74HC640M96的Datasheet PDF文件第7页 
CD54HC640, CD74HC640,  
CD54HCT640, CD74HCT640  
Data sheet acquired from Harris Semiconductor  
SCHS192B  
High-Speed CMOS Logic  
Octal Three-State Bus Transceiver, Inverting  
January 1998 - Revised May 2003  
Features  
Description  
• Buffered Inputs  
The ’HC640 and ’HCT640 silicon-gate CMOS three-state  
bidirectional inverting and non-inverting buffers are intended  
for two-way asynchronous communication between data  
buses. They have high drive current outputs which enable  
high-speed operation when driving large bus capacitances.  
These circuits possess the low power dissipation of CMOS  
• Three-State Outputs  
[ /Title  
(CD74  
HC640  
,
• Applications in Multiple-Data-Bus Architecture  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
circuits, and have speeds comparable to low power Schottky  
CD74  
HCT64  
0)  
/Sub-  
ject  
(High  
Speed  
CMOS  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TTL circuits. They can drive 15 LSTTL loads. The ’HC640  
and ’HCT640 are inverting buffers.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
The direction of data flow (A to B, B to A) is controlled by the  
DIR input.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Outputs are enabled by a low on the Output Enable input  
(OE); a high OE puts these devices in the high impedance  
mode.  
• HC Types  
- 2V to 6V Operation  
Ordering Information  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
TEMP. RANGE  
o
PART NUMBER  
CD54HC640F3A  
CD54HCT640F3A  
CD74HC640E  
( C)  
PACKAGE  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld PDIP  
• HCT Types  
- 4.5V to 5.5V Operation  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
CD74HC640M  
20 Ld SOIC  
Pinout  
CD74HCT640E  
CD74HCT640M  
20 Ld PDIP  
CD54HC640, CD54HCT640  
(CERDIP)  
20 Ld SOIC  
CD74HC640, CD74HCT640  
(PDIP, SOIC)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
V
DIR  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
20  
19  
CC  
OE  
18 B0  
17 B1  
16 B2  
15 B3  
14 B4  
13 B5  
12  
B6  
GND 10  
11 B7  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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