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CD74HC533E PDF预览

CD74HC533E

更新时间： 2024-11-01 23:00:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器
页数 文件大小 规格书
9页 53K
描述
High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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中文翻译

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CD74HC533E 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：DIP
包装说明：DIP-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.05Is Samacsys：N
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：HC/UHJESD-30 代码：R-PDIP-T20
JESD-609代码：e4长度：24.33 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.0078 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：50 ns传播延迟（tpd）：265 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.35 mmBase Number Matches：1

CD74HC533E 数据手册

 浏览型号CD74HC533E的Datasheet PDF文件第2页浏览型号CD74HC533E的Datasheet PDF文件第3页浏览型号CD74HC533E的Datasheet PDF文件第4页浏览型号CD74HC533E的Datasheet PDF文件第5页浏览型号CD74HC533E的Datasheet PDF文件第6页浏览型号CD74HC533E的Datasheet PDF文件第7页 
CD74HC533, CD74HCT533,  
CD74HC563, CD74HCT563  
Data sheet acquired from Harris Semiconductor  
SCHS187  
High Speed CMOS Logic Octal Inverting  
Transparent Latch, Three-State Outputs  
January 1998  
Features  
Description  
• Common Latch-Enable Control  
• Common Three-State Output Enable Control  
• Buffered Inputs  
The Harris CD74HC533, CD74HCT533, CD74HC563, and  
CD74HCT563 are high speed Octal Transparent Latches  
manufactured with silicon gate CMOS technology. They pos-  
sess the low power consumption of standard CMOS inte-  
grated circuits, as well as the ability to drive 15 LSTTL  
devices.  
[ /Title  
(CD74H  
C533,  
CD74H  
CT533,  
CD74H  
C563,  
CD74H  
CT563)  
/Subject  
(High  
• Three-State Outputs  
• Bus Line Driving Capacity  
The outputs are transparent to the inputs when the latch  
enable (LE) is high. When the latch enable (LE) goes low the  
data is latched. The output enable (OE) controls the three-  
state outputs. When the output enable (OE) is high the  
outputs are in the high impedance state. The latch operation  
• Typical Propagation Delay = 13ns at V  
CC  
= 5V,  
o
C = 15pF, T = 25 C (Data to Output)  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
is independent to the state of the output enable.  
The CD74HC533 and CD74HCT533 are identical in function  
to the CD74HC563 and CD74HCT563 but have different  
pinouts. The CD74HC533 and CD74HCT533 are similar to  
the CD74HC373 and CD74HCT373; the latter are non-  
inverting types.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Speed  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Ordering Information  
• HC Types  
- 2V to 6V Operation  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC533E  
CD74HCT533E  
CD74HC563E  
CD74HCT563E  
CD74HCT563M  
NOTES:  
( C)  
PACKAGE  
20 Ld PDIP  
20 Ld PDIP  
20 Ld PDIP  
20 Ld PDIP  
20 Ld SOIC  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
F20.3  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
E20.3  
E20.3  
E20.3  
M20.3  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer and die for this part number are available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1599.1  
Copyright © Harris Corporation 1998  
1
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中文翻译

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CD74HC533E 替代型号

型号 品牌 替代类型 描述 数据表
CD54HC533F3A TI

完全替代

 High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
SN74AC533N TI

类似代替

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
CD74HC533EE4 TI

类似代替

 High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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 		High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggere
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 		High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggere
CD74HC534E ROCHESTER

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 		HC/UH SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20

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