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CD74HC533

更新时间: 2024-11-01 23:00:39
品牌 Logo 应用领域
德州仪器 - TI 锁存器
页数 文件大小 规格书
9页 53K
描述
High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

CD74HC533 数据手册

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CD74HC533, CD74HCT533,  
CD74HC563, CD74HCT563  
Data sheet acquired from Harris Semiconductor  
SCHS187  
High Speed CMOS Logic Octal Inverting  
Transparent Latch, Three-State Outputs  
January 1998  
Features  
Description  
• Common Latch-Enable Control  
• Common Three-State Output Enable Control  
• Buffered Inputs  
The Harris CD74HC533, CD74HCT533, CD74HC563, and  
CD74HCT563 are high speed Octal Transparent Latches  
manufactured with silicon gate CMOS technology. They pos-  
sess the low power consumption of standard CMOS inte-  
grated circuits, as well as the ability to drive 15 LSTTL  
devices.  
[ /Title  
(CD74H  
C533,  
CD74H  
CT533,  
CD74H  
C563,  
CD74H  
CT563)  
/Subject  
(High  
• Three-State Outputs  
• Bus Line Driving Capacity  
The outputs are transparent to the inputs when the latch  
enable (LE) is high. When the latch enable (LE) goes low the  
data is latched. The output enable (OE) controls the three-  
state outputs. When the output enable (OE) is high the  
outputs are in the high impedance state. The latch operation  
• Typical Propagation Delay = 13ns at V  
CC  
= 5V,  
o
C = 15pF, T = 25 C (Data to Output)  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
is independent to the state of the output enable.  
The CD74HC533 and CD74HCT533 are identical in function  
to the CD74HC563 and CD74HCT563 but have different  
pinouts. The CD74HC533 and CD74HCT533 are similar to  
the CD74HC373 and CD74HCT373; the latter are non-  
inverting types.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Speed  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Ordering Information  
• HC Types  
- 2V to 6V Operation  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC533E  
CD74HCT533E  
CD74HC563E  
CD74HCT563E  
CD74HCT563M  
NOTES:  
( C)  
PACKAGE  
20 Ld PDIP  
20 Ld PDIP  
20 Ld PDIP  
20 Ld PDIP  
20 Ld SOIC  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
F20.3  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
E20.3  
E20.3  
E20.3  
M20.3  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer and die for this part number are available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1599.1  
Copyright © Harris Corporation 1998  
1

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