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CD74HC4075PW PDF预览

CD74HC4075PW

更新时间: 2024-11-19 23:07:31
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 348K
描述
High-Speed CMOS Logic Triple 3-Input OR Gate

CD74HC4075PW 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.05Is Samacsys:N
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:OR GATE
最大I(ol):0.0052 A湿度敏感等级:1
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/6 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):150 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

CD74HC4075PW 数据手册

 浏览型号CD74HC4075PW的Datasheet PDF文件第2页浏览型号CD74HC4075PW的Datasheet PDF文件第3页浏览型号CD74HC4075PW的Datasheet PDF文件第4页浏览型号CD74HC4075PW的Datasheet PDF文件第5页浏览型号CD74HC4075PW的Datasheet PDF文件第6页浏览型号CD74HC4075PW的Datasheet PDF文件第7页 
CD54HC4075, CD74HC4075,  
CD54HCT4075, CD74HCT4075  
Data sheet acquired from Harris Semiconductor  
SCHS210F  
High-Speed CMOS Logic  
Triple 3-Input OR Gate  
August 1997 - Revised August 2003  
Features  
Description  
• Buffered Inputs  
The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate  
CMOS technology to achieve operating speeds similar to  
LSTTL gates with the low power consumption of standard  
CMOS integrated circuits. All devices have the ability to drive  
10 LSTTL loads. The HCT logic family is functionally pin  
compatible with the standard LS logic family.  
• Typical Propagation Delay: 8ns at V  
o
= 5V,  
[ /Title  
(CD74H  
C4075,  
CD74H  
CT4075)  
/Subject  
(High  
Speed  
CMOS  
Logic  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC4075F3A  
CD54HCT4075F3A  
CD74HC4075E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
Triple 3-  
Input  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC4075M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
at V  
= 5V  
CC  
CD74HC4075MT  
CD74HC4075M96  
CD74HC4075NSR  
CD74HC4075PW  
CD74HC4075PWR  
CD74HC4075PWT  
CD74HCT4075E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Pinout  
CD54HC4075, CD54HCT4075 (CERDIP)  
CD74HC4075 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT4075 (PDIP)  
TOP VIEW  
2A  
2B  
1
2
3
4
5
6
7
14 V  
CC  
13 3C  
12 3B  
11 3A  
10 3Y  
1A  
1B  
1C  
1Y  
9
8
2Y  
2C  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD74HC4075PW 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC4075PWTE4 TI

完全替代

High Speed CMOS Logic Triple 3-Input OR Gate
CD74HC4075PWRE4 TI

完全替代

High Speed CMOS Logic Triple 3-Input OR Gate
CD74HC4075PWT TI

完全替代

High-Speed CMOS Logic Triple 3-Input OR Gate

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