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CD74HC4075

更新时间： 2024-11-19 23:07:31
品牌 Logo 应用领域
德州仪器 - TI 栅
页数 文件大小 规格书
6页 36K
描述
High Speed CMOS Logic Triple 3-Input OR Gate

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CD74HC4075 数据手册

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CD74HC4075,  
CD74HCT4075  
Data sheet acquired from Harris Semiconductor  
SCHS210  
High Speed CMOS Logic  
Triple 3-Input OR Gate  
August 1997  
Features  
Description  
• Buffered Inputs  
The Harris CD74HC4075, CD74HCT4075 logic gates utilize  
silicon-gate CMOS technology to achieve operating speeds  
similar to LSTTL gates with the low power consumption of  
standard CMOS integrated circuits. All devices have the  
ability to drive 10 LSTTL loads. The 74HCT logic family is  
functionally pin compatible with the standard 74LS logic  
family.  
• Typical Propagation Delay: 8ns at V  
o
= 5V,  
[ /Title  
(CD74H  
C4075,  
CD74H  
CT4075)  
/Subject  
(High  
Speed  
CMOS  
Logic  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
PKG.  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
NO.  
E14.3  
E14.3  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
CD74HC4075E  
CD74HC4075E  
CD74HC4075M  
CD74HC4075M  
CD54HC4075H  
CD54HCT4075H  
CD54HC4075W  
CD54HCT4075W  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
14 Ld PDIP  
14 Ld PDIP  
• HC Types  
Triple 3-  
Input  
- 2V to 6V Operation  
14 Ld SOIC M14.15  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
14 Ld SOIC M14.15  
• HCT Types  
Die  
- 4.5V to 5.5V Operation  
Die  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
Wafer  
Wafer  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. Add the suffix 96  
to obtain the variant in the tape and reel.  
Pinout  
CD74HC4075, CD74HCT4075  
(PDIP, SOIC)  
TOP VIEW  
2A  
2B  
1
2
3
4
5
6
7
14 V  
CC  
13 3C  
12 3B  
11 3A  
10 3Y  
1A  
1B  
1C  
1C  
9
8
2Y  
2C  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1778.1  
Copyright © Harris Corporation 1997  
1
123456

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CD74HC4075 替代型号

型号 品牌 替代类型 描述 数据表
CD54HC4075 TI

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 High-Speed CMOS Logic Triple 3-Input OR Gate

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