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CD74HC4049M PDF预览

CD74HC4049M

更新时间： 2024-01-30 07:43:04
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德州仪器 - TI 栅极
页数 文件大小 规格书
5页 31K
描述
High-Speed CMOS Logic Hex Buffers, Inverting and Non-Inverting

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CD74HC4049M 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.26
Is Samacsys：N其他特性：CMOS-TTL LEVEL TRANSLATOR
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：INVERTER
最大I（ol）：0.004 A湿度敏感等级：1
功能数量：6输入次数：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：2/6 VProp。Delay @ Nom-Sup：26 ns
传播延迟（tpd）：130 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：1.2 mm
子类别：Gates最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

CD74HC4049M 数据手册

 浏览型号CD74HC4049M的Datasheet PDF文件第2页浏览型号CD74HC4049M的Datasheet PDF文件第3页浏览型号CD74HC4049M的Datasheet PDF文件第4页浏览型号CD74HC4049M的Datasheet PDF文件第5页 
CD74HC4049,  
CD74HC4050  
Data sheet acquired from Harris Semiconductor  
SCHS205A  
High-Speed CMOS Logic  
February 1998 - Revised June 1999  
Hex Buffers, Inverting and Non-Inverting  
Features  
Description  
• Typical Propagation Delay: 6ns at V  
o
= 5V,  
The CD74HC4049 and CD74HC4050 are fabricated with  
high-speed silicon gate technology. They have a modified  
input protection structure that enables these parts to be  
used as logic level translators which convert high-level logic  
to a low-level logic while operating off the low-level logic  
supply. For example, 15-V input pulse levels can be down-  
converted to 0-V to 5-V logic levels. The modified input  
protection structure protects the input from negative  
CC  
C = 15pF, T = 25 C  
L
A
[ /Title  
(CD74H  
C4049,  
CD74H  
C4050)  
/Sub-  
• High-to-Low Voltage Level Converter for up to V = 16V  
l
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . .–55 C to 125 C electrostatic discharge. These parts also can be used as  
simple buffers or inverters without level translation. The  
CD74HC4049 and CD74HC4050 are enhanced versions of  
ject  
• Balanced Propagation Delay and Transition Times  
(High  
Speed  
CMOS  
Logic  
Hex  
equivalent CMOS types.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Ordering Information  
• HC Types  
- 2V to 6V Operation  
TEMP. RANGE  
o
PKG.  
NO.  
PART NUMBER  
CD74HC4049E  
CD74HC4050E  
CD74HC4049M  
CD74HC4050M  
CD74HC4050PW  
NOTES:  
( C)  
PACKAGE  
16 Ld PDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld TSSOP  
- High Noise Immunity: N = 30%, N = 30%of V  
IL IH CC  
at  
V
= 5V  
CC  
–55 to 125  
–55 to 125  
–55 to 125  
–55 to 125  
–55 to 125  
E16.3  
E16.3  
M16.15  
M16.15  
1. When ordering, use the entire part number. Add the suffix 96 to  
the M suffix or the R suffix to the PW package to obtain the  
variant in the tape and reel.  
2. Wafer and die is available which meets all electrical  
specifications. Please contact your local sales office or  
customer service for ordering information.  
Pinout  
CD74HC4049, CD74HC4050  
(PDIP, SOIC, TSSOP)  
TOP VIEW  
4049 4050  
4050  
16 NC  
4049  
NC  
V
V
1
2
3
4
5
6
7
8
CC  
1Y  
CC  
1Y  
15 6Y  
14 6A  
13 NC  
12 5Y  
11 5A  
10 4Y  
6Y  
6A  
NC  
5Y  
5A  
4Y  
4A  
1A  
2Y  
2A  
3Y  
3A  
1A  
2Y  
2A  
3Y  
3A  
9
4A  
GND GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 1999 Texas Instruments Incorporated  
1
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