CD74HC390,
CD74HCT390
Data sheet acquired from Harris Semiconductor
SCHS185
High Speed CMOS Logic
September 1997
Dual Decade Ripple Counter
Features
Description
• Two BCD Decade or Bi-Quinary Counters
The Harris CD74HC390 and CD574HCT390 dual 4-bit
decade ripple counters are high-speed silicon-gate CMOS
devices and are pin compatible with low-power Schottky TTL
(LSTTL). These devices are divided into four separately
clocked sections. The counters have two divide-by-2 sec-
tions and two divide-by-5 sections. These sections are nor-
mally used in a BCD decade or bi-quinary configuration,
since they share a common master reset (nMR). If the two
master reset inputs (1MR and 2MR) are used to simulta-
neously clear all 8 bits of the counter, a number of counting
configurations are possible within one package. The sepa-
rate clock inputs (nCP0 and nCP1) of each section allow rip-
ple counter or frequency division applications of divide-by-2,
4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the
High-to-Low transition of the input pulses (nCP0 and nCP1).
• One Package Can Be Configured to Divide-by-2, 4,
5,10, 20, 25, 50 or 100
[ /Title
(CD74
HC390
,
CD74
HCT39
0)
/Sub-
ject
(High
Speed
CMOS
• Two Master Reset Inputs to Clear Each Decade
Counter Individually
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
For BCD decade operation, the nQ0 output is connected to
the nCP1 input of the divide-by-5 section. For bi-quinary
decade operation, the nO3 output is connected to the nCP0
• HC Types
- 2V to 6V Operation
input and nQ becomes the decade output.
0
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
The master reset inputs (1MR and 2MR) are active-High
asynchronous inputs to each decade counter which oper-
ates on the portion of the counter identified by the “1” and “2”
prefixes in the pin configuration. A High level on the nMR
input overrides the clock and sets the four outputs Low.
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
Ordering Information
l
OL OH
PKG.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E16.3
E16.3
Pinout
CD74HC390E
CD74HCT390E
CD74HC390M
CD74HCT390M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
CD74HC390, CD74HCT390
TOP VIEW
1CP0
1MR
1
2
3
4
5
6
7
8
16 V
CC
16 Ld SOIC M16.15
16 Ld SOIC M16.15
15 2CP0
14 2MR
13 2Q0
1Q
0
1CP1
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
1Q
1Q
1Q
12 2CP1
1
2
3
11 2Q
10 2Q
1
2
3
2. Wafer for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
9
2Q
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1838.2
Copyright © Harris Corporation 1997
1