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CD74HC373M96 PDF预览

CD74HC373M96

更新时间： 2024-11-19 23:00:39
品牌 Logo 应用领域
德州仪器 - TI 锁存器逻辑集成电路光电二极管输出元件驱动
页数 文件大小 规格书
9页 310K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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CD74HC373M96 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.69控制类型：ENABLE LOW/HIGH
计数方向：UNIDIRECTIONAL系列：HC/UH
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.0078 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TR峰值回流温度（摄氏度）：260
电源：2/6 V最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：45 ns传播延迟（tpd）：265 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.5 mm
Base Number Matches：1

CD74HC373M96 数据手册

 浏览型号CD74HC373M96的Datasheet PDF文件第2页浏览型号CD74HC373M96的Datasheet PDF文件第3页浏览型号CD74HC373M96的Datasheet PDF文件第4页浏览型号CD74HC373M96的Datasheet PDF文件第5页浏览型号CD74HC373M96的Datasheet PDF文件第6页浏览型号CD74HC373M96的Datasheet PDF文件第7页 
CD54HC373, CD74HC373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003  
CD54HC373 . . . F PACKAGE  
CD74HC373 . . . E OR M PACKAGE  
(TOP VIEW)  
2-V to 6-V V  
Operation  
CC  
Wide Operating Temperature Range of  
–55°C to 125°C  
Balanced Propagation Delays and  
Transition Times  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
Standard Outputs Drive up to 15 LS-TTL  
Loads  
Significant Power Reduction Compared to  
LS-TTL Logic ICs  
description/ordering information  
The ’HC373 devices are octal transparent D-type  
GND  
latches designed for 2-V to 6-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs  
are latched at the logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74HC373E  
CD74HC373E  
CD74HC373M  
CD74HC373M96  
CD54HC373F3A  
–55°C to 125°C  
SOIC – M  
HC373M  
Tape and reel  
Tube  
CDIP – F  
CD54HC373F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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CD74HC373M96 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC373ADWR2 ONSEMI

完全替代

 Octal 3-State Non-Inverting Transparent Latch
SN74HC373DWRE4 TI

类似代替

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
CD74HC373M TI

类似代替

 High Speed CMOS Logic Octal Transparent Latch, Three-State Output

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