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CD74HC367M96G4 PDF预览

CD74HC367M96G4

更新时间： 2024-09-09 05:09:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
16页 430K
描述
High-Speed CMOS Logic Hex Buffer/Line Driver,Three-State Non-Inverting and Inverting

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CD74HC367M96G4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.08其他特性：ONE FUNCTION WITH TWO BITS
控制类型：ENABLE LOW系列：HC/UH
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.006 A
湿度敏感等级：1位数：4
功能数量：2端口数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：2/6 VProp。Delay @ Nom-Sup：32 ns
传播延迟（tpd）：160 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

CD74HC367M96G4 数据手册

 浏览型号CD74HC367M96G4的Datasheet PDF文件第2页浏览型号CD74HC367M96G4的Datasheet PDF文件第3页浏览型号CD74HC367M96G4的Datasheet PDF文件第4页浏览型号CD74HC367M96G4的Datasheet PDF文件第5页浏览型号CD74HC367M96G4的Datasheet PDF文件第6页浏览型号CD74HC367M96G4的Datasheet PDF文件第7页 
CD54/74HC367, CD54/74HCT367,  
CD54/74HC368, CD74HCT368  
Data sheet acquired from Harris Semiconductor  
SCHS181D  
High-Speed CMOS Logic Hex Buffer/Line Driver,  
Three-State Non-Inverting and Inverting  
November 1997 - Revised October 2003  
Features  
Ordering Information  
TEMP. RANGE  
o
• Buffered Inputs  
PART NUMBER  
CD54HC367F3A  
CD54HC368F3A  
CD54HCT367F3A  
CD74HC367E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
• High Current Bus Driver Outputs  
• Two Independent Three-State Enable Controls  
[ /Title  
(CD74  
HC367  
,
CD74  
HCT36  
7,  
CD74  
HC368  
,
CD74  
HCT36  
8)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Typical Propagation Delay t  
, t  
= 8ns at V = 5V,  
CC  
PLH PHL  
o
C = 15pF, T = 25 C  
L
A
CD74HC367M  
• Fanout (Over Temperature Range)  
CD74HC367MT  
CD74HC367M96  
CD74HC368E  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74HC368M  
CD74HC368MT  
CD74HC368M96  
CD74HCT367E  
CD74HCT367M  
CD74HCT367MT  
CD74HCT367M96  
CD74HCT368E  
CD74HCT368M  
CD74HCT368MT  
CD74HCT368M96  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
/Sub-  
ject  
(High  
Speed  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Description  
The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate  
CMOS three-state buffers are general purpose high-speed  
non-inverting and inverting buffers. They have high drive cur-  
rent outputs which enable high speed operation even when  
driving large bus capacitances. These circuits possess the low  
power dissipation of CMOS circuitry, yet have speeds compara-  
ble to low power Schottky TTL circuits. Both circuits are capable  
of driving up to 15 low power Schottky inputs.  
The ’HC367 and ’HCT367 are non-inverting buffers, whereas  
the ’HC368 and CD74HCT368 are inverting buffers. These  
devices have two output enables, one enable (OE1) controls 4  
gates and the other (OE2) controls the remaining 2 gates.  
The ’HCT367 and CD74HCT368 logic families are speed, func-  
tion and pin compatible with the standard LS logic family.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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CD74HC368E TI

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