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CD74HC32M PDF预览

CD74HC32M

更新时间: 2024-11-23 23:00:39
品牌 Logo 应用领域
德州仪器 - TI 栅极
页数 文件大小 规格书
6页 38K
描述
High Speed CMOS Logic Quad 2-Input OR Gate

CD74HC32M 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.6系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.0052 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:2/6 V
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):135 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.91 mmBase Number Matches:1

CD74HC32M 数据手册

 浏览型号CD74HC32M的Datasheet PDF文件第2页浏览型号CD74HC32M的Datasheet PDF文件第3页浏览型号CD74HC32M的Datasheet PDF文件第4页浏览型号CD74HC32M的Datasheet PDF文件第5页浏览型号CD74HC32M的Datasheet PDF文件第6页 
CD54HCT32, CD74HC32,  
CD74HCT32  
Data sheet acquired from Harris Semiconductor  
SCHS274  
High Speed CMOS Logic  
Quad 2-Input OR Gate  
September 1997  
Features  
Description  
• Typical Propagation Delay: 7ns at V  
o
= 5V,  
The Harris CD74HC32, CD74HCT32 contain four 2-input OR  
gates in one package. Logic gates utilize silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The 74HCT logic family is functionally pin  
compatible with the standard 74LS logic family.  
CC  
C = 15pF, T = 25 C  
L
A
[ /Title  
(CD54  
HCT32  
,
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74  
HC32,  
CD74  
HCT32  
)
/Sub-  
ject  
(High  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC32E  
CD74HCT32E  
CD74HC32M  
CD74HCT32M  
CD54HCT32F  
CD54HC32W  
NOTES:  
( C)  
PACKAGE  
14 Ld PDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
• HC Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
E14.3  
- 2V to 6V Operation  
E14.3  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
at V  
= 5V  
CC  
M14.15  
M14.15  
• HCT Types  
- 4.5V to 5.5V Operation  
14 Ld CERDIP F14.3  
Wafer  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
• Related Literature  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
- CD54HC32F3A and CD54HCT32F3A Military  
Data Sheet, Document Number 3765  
2. Die for this part number is available which meets all electrical  
specifications. Please contact your local sales office or Harris  
customer service for ordering information.  
Pinout  
CD54HCT32, CD74HC32, CD74HCT32  
(PDIP, CERDIP, SOIC)  
TOP VIEW  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
13 4B  
12 4A  
11 4Y  
10 3B  
1Y  
2A  
2B  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1643.2  
Copyright © Harris Corporation 1997  
1

CD74HC32M 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC32MT TI

完全替代

High-Speed CMOS Logic Quad 2-Input OR Gate
SN74HC32N TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN74HC32DR TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-OR GATES

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