CD74HC297

更新时间： 2024-01-27 06:21:09

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
11页	99K
描述
High-Speed CMOS Logic Digital Phase-Locked-Loop

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CD74HC297 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.73
Is Samacsys：	N	系列：	HC/UH
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
逻辑集成电路类型：	LOGIC CIRCUIT	功能数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

CD74HC297 数据手册

CD74HC297,

CD74HCT297

Data sheet acquired from Harris Semiconductor

SCHS177

High-Speed CMOS Logic

Digital Phase-Locked-Loop

November 1997

Features

Description

• Digital Design Avoids Analog Compensation Errors

• Easily Cascadable for Higher Order Loops

The Harris CD74HC297 and CD74HCT297 are high-speed

silicon gate CMOS devices that are pin-compatible with low

power Schottky TTL (LSTTL).

[ /Title

(CD74

HC297

CD74

HCT29

• Useful Frequency Range

These devices are designed to provide a simple, cost-effec-

tive solution to high-accuracy, digital, phase-locked-loop appli-

cations. They contain all the necessary circuits, with the

exception of the divide-by-N counter, to build first-order

phase-locked-loops.

- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)

- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)

• Dynamically Variable Bandwidth

• Very Narrow Bandwidth Attainable

• Power-On Reset

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase

detectors (ECPD) are provided for maximum flexibility. The

input signals for the EXCLUSIVE-OR phase detector must

have a 50% duty factor to obtain the maximum lock-range.

/Sub-

ject

• Output Capability

- Standard. . . . . . . . . . . . . . . . . . . . XORPD

, ECPD

OUT

(High-

Speed

CMOS

Logic

Digi-

tal

Proper partitioning of the loop function, with many of the build-

ing blocks external to the package, makes it easy for the

designer to incorporate ripple cancellation (see Figure 2) or to

cascade to higher order phase-locked-loops.

- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

The length of the up/down K-counter is digitally programmable

according to the K-counter function table. With A, B, C and D

all LOW, the K-counter is disabled. With A HIGH and B, C and

D LOW, the K-counter is only three stages long, which widens

the bandwidth or capture range and shortens the lock time of

the loop. When A, B, C and D are all programmed HIGH, the

K-counter becomes seventeen stages long, which narrows

the bandwidth or capture range and lengthens the lock time.

Real-time control of loop bandwidth by manipulating the A to

D inputs can maximize the overall performance of the digital

phase-locked-loop.

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

Phase-

Locked

• CD74HC297 Types

- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V

- High Noise ImmunityN = 30%, N = 30% of V at 5V

IL IH CC

• CD74HCT297 Types

- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V

- Direct LSTTL Input Logic Compatibility

The CD74HC297 and CD74HCT297 can perform the classic

first order phase-locked-loop function without using analog

components. The accuracy of the digital phase-locked-loop

= 0.8V (Max), V = 2V (Min)

- CMOS Input Compatibility I ≤ 1µA at V , V

OL OH

(DPLL) is not affected by V

depends solely on accuracies of the K-clock and loop propa-

gation delays.

and temperature variations but

Ordering Information

PKG.

NO.

PART NUMBER TEMP. RANGE ( C) PACKAGE

CD74HC297E

CD74HCT297E

NOTES:

-55 to 125

16 Ld PDIP

E16.3

Pinout

CD74HC297, CD74HCT297 (PDIP)

TOP VIEW

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

16 V

15 C

14 D

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

CTR

13 φA

I/D

12 ECPD

OUT

D/U

11 XORPD

OUT

10 φB

I/D

OUT

φA

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1852.1

12 3 4 5 6 7...11

中文翻译

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CD74HC297 替代型号

型号	品牌	替代类型	描述	数据表
CD54HC297	TI	功能相似	High-Speed CMOS Logic Digital Phase-Locked Loop

与CD74HC297相关器件

型号	品牌	获取价格	描述	数据表
CD74HC297E	RENESAS	获取价格	IC,PHASE-LOCKED LOOP,HC-CMOS,DIP,16PIN,PLASTIC
CD74HC297E	TI	获取价格	High-Speed CMOS Logic Digital Phase-Locked-Loop
CD74HC297E96	RENESAS	获取价格	SPECIALTY LOGIC CIRCUIT, PDIP16, PLASTIC, DIP-16
CD74HC297EE4	TI	获取价格	High-Speed CMOS Logic Digital Phase-Locked Loop
CD74HC297EN	ETC	获取价格	Analog IC
CD74HC297EX	RENESAS	获取价格	CD74HC297EX
CD74HC297F	ETC	获取价格	Analog IC
CD74HC297H	ETC	获取价格	Analog Phase-Locked Loop
CD74HC297M	ETC	获取价格	Analog IC
CD74HC299	TI	获取价格	High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

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