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CD74HC195PWRG4 PDF预览

CD74HC195PWRG4

更新时间： 2024-09-29 05:18:15
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管输出元件输入元件
页数 文件大小 规格书
16页 632K
描述
High-Speed CMOS Logic 4-Bit Parallel Access Register

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中文翻译

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CD74HC195PWRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.26Is Samacsys：N
其他特性：COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT计数方向：RIGHT
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
逻辑集成电路类型：PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup：20000000 Hz
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：265 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：23 MHz
Base Number Matches：1

CD74HC195PWRG4 数据手册

 浏览型号CD74HC195PWRG4的Datasheet PDF文件第2页浏览型号CD74HC195PWRG4的Datasheet PDF文件第3页浏览型号CD74HC195PWRG4的Datasheet PDF文件第4页浏览型号CD74HC195PWRG4的Datasheet PDF文件第5页浏览型号CD74HC195PWRG4的Datasheet PDF文件第6页浏览型号CD74HC195PWRG4的Datasheet PDF文件第7页 
CD54HC195, CD74HC195  
Data sheet acquired from Harris Semiconductor  
SCHS165E  
High-Speed CMOS Logic  
4-Bit Parallel Access Register  
September 1997 - Revised October 2003  
Features  
Description  
• Asynchronous Master Reset  
• J, K, (D) Inputs to First Stage  
• Fully Synchronous Serial or Parallel Data Transfer  
• Shift Right and Parallel Load Capability  
• Complementary Output From Last Stage  
• Buffered Inputs  
The device is useful in a wide variety of shifting, counting  
and storage applications. It performs serial, parallel, serial to  
parallel, or parallel to serial data transfers at very high  
speeds.  
[ /Title  
(CD74  
HC195  
)
/Sub-  
ject  
(High  
Speed  
CMOS  
Logic  
4-Bit  
Paral-  
lel  
The two modes of operation, shift right (Q -Q ) and parallel  
0
1
load, are controlled by the state of the Parallel Enable (PE)  
input. Serial data enters the first flip-flop (Q ) via the J and K  
0
inputs when the PE input is high, and is shifted one bit in the  
direction Q -Q -Q -Q following each Low to High clock  
0
1
2
3
• Typical f  
MAX  
= 50MHz at V = 5V,  
CC  
transition. The J and K inputs provide the flexibility of the JK-  
type input for special applications and by tying the two pins  
together, the simple D-type input for general applications.  
The device appears as four common-clocked D flip-flops  
when the PE input is Low. After the Low to High clock  
transition, data on the parallel inputs (D0-D3) is transferred  
to the respective Q -Q outputs. Shift left operation (Q -Q )  
o
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
0
3
3
2
can be achieved by tying the Q outputs to the Dn-1 inputs  
n
and holding the PE input low.  
Access  
Regis-  
ter)  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
All parallel and serial data transfers are synchronous, occurring  
after each Low to High clock transition. The ’HC195 series  
utilizes edge triggering; therefore, there is no restriction on the  
activity of the J, K, Pn and PE inputs for logic operations, other  
than set-up and hold time requirements. A Low on the  
asynchronous Master Reset (MR) input sets all Q outputs Low,  
independent of any other input condition.  
• HC Types  
/Autho  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30%of V  
at  
IL  
IH  
CC  
V
= 5V  
CC  
Ordering Information  
PInout  
TEMP. RANGE  
o
PART NUMBER  
CD54HC195F3A  
CD74HC195E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
CD54HC195  
(CERDIP)  
CD74HC195  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
(PDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
CD74HC195M  
16 Ld SOIC  
MR  
J
1
2
3
4
5
6
7
8
16 V  
CC  
CD74HC195NSR  
CD74HC195PW  
CD74HC195PWR  
CD74HC195PWT  
16 Ld SOP  
15 Q  
14 Q  
13 Q  
12 Q  
11 Q  
0
1
2
3
3
K
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
D0  
D1  
D2  
D3  
GND  
NOTE: When ordering, use the entire part number. The suffix R  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
10 CP  
PE  
9
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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中文翻译

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CD74HC195PWRG4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC195PWG4 TI

完全替代

 High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWT TI

完全替代

 High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PW TI

完全替代

 High-Speed CMOS Logic 4-Bit Parallel Access Register

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