CD74HC195MG4

更新时间： 2024-09-29 05:18:15

品牌	Logo	应用领域
德州仪器 - TI		移位寄存器触发器逻辑集成电路光电二极管输出元件输入元件
页数	文件大小	规格书
16页	632K
描述
High-Speed CMOS Logic 4-Bit Parallel Access Register

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技术参数
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CD74HC195MG4 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOP, SOP16,.25
针数：	16	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.12
Is Samacsys：	N	其他特性：	COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT
计数方向：	RIGHT	系列：	HC/UH
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e4
长度：	9.9 mm	逻辑集成电路类型：	PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup：	20000000 Hz	湿度敏感等级：	1
位数：	4	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	2/6 V	传播延迟（tpd）：	265 ns
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Shift Registers	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	4.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
触发器类型：	POSITIVE EDGE	宽度：	3.9 mm
最小 fmax：	23 MHz	Base Number Matches：	1

CD74HC195MG4 数据手册

CD54HC195, CD74HC195

Data sheet acquired from Harris Semiconductor

SCHS165E

High-Speed CMOS Logic

4-Bit Parallel Access Register

September 1997 - Revised October 2003

Features

Description

• Asynchronous Master Reset

• J, K, (D) Inputs to First Stage

• Fully Synchronous Serial or Parallel Data Transfer

• Shift Right and Parallel Load Capability

• Complementary Output From Last Stage

• Buffered Inputs

The device is useful in a wide variety of shifting, counting

and storage applications. It performs serial, parallel, serial to

parallel, or parallel to serial data transfers at very high

speeds.

[ /Title

(CD74

HC195

)

/Sub-

ject

(High

Speed

CMOS

Logic

4-Bit

Paral-

lel

The two modes of operation, shift right (Q -Q ) and parallel

load, are controlled by the state of the Parallel Enable (PE)

input. Serial data enters the ﬁrst ﬂip-ﬂop (Q ) via the J and K

inputs when the PE input is high, and is shifted one bit in the

direction Q -Q -Q -Q following each Low to High clock

• Typical f

MAX

= 50MHz at V = 5V,

transition. The J and K inputs provide the ﬂexibility of the JK-

type input for special applications and by tying the two pins

together, the simple D-type input for general applications.

The device appears as four common-clocked D ﬂip-ﬂops

when the PE input is Low. After the Low to High clock

transition, data on the parallel inputs (D0-D3) is transferred

to the respective Q -Q outputs. Shift left operation (Q -Q )

C = 15pF, T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

can be achieved by tying the Q outputs to the Dn-1 inputs

and holding the PE input low.

Access

Regis-

ter)

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

All parallel and serial data transfers are synchronous, occurring

after each Low to High clock transition. The ’HC195 series

utilizes edge triggering; therefore, there is no restriction on the

activity of the J, K, Pn and PE inputs for logic operations, other

than set-up and hold time requirements. A Low on the

asynchronous Master Reset (MR) input sets all Q outputs Low,

independent of any other input condition.

• HC Types

/Autho

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30%of V

= 5V

Ordering Information

PInout

TEMP. RANGE

PART NUMBER

CD54HC195F3A

CD74HC195E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

CD54HC195

(CERDIP)

CD74HC195

-55 to 125

(PDIP, SOIC, SOP, TSSOP)

TOP VIEW

CD74HC195M

16 Ld SOIC

16 V

CD74HC195NSR

CD74HC195PW

CD74HC195PWR

CD74HC195PWT

16 Ld SOP

15 Q

14 Q

13 Q

12 Q

11 Q

16 Ld TSSOP

GND

NOTE: When ordering, use the entire part number. The sufﬁx R

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

10 CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...16

中文翻译

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CD74HC195MG4 替代型号

型号	品牌	替代类型	描述	数据表
CD74HC195M96G4	TI	完全替代	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195M96	TI	完全替代	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195NSR	TI	完全替代	High-Speed CMOS Logic 4-Bit Parallel Access Register

与CD74HC195MG4相关器件

型号	品牌	获取价格	描述	数据表
CD74HC195NSR	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195NSRE4	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195NSRG4	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PW	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWE4	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWG4	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWR	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWRE4	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWRG4	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD74HC195PWT	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register

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