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CD74HC123NSRG4 PDF预览

CD74HC123NSRG4

更新时间: 2024-11-01 05:18:11
品牌 Logo 应用领域
德州仪器 - TI 预分频器多谐振动器触发器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
19页 512K
描述
High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

CD74HC123NSRG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.01
Is Samacsys:N其他特性:RETRIGGERABLE
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:10.2 mm
逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR湿度敏感等级:1
数据/时钟输入次数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):480 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Prescaler/Multivibrators最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

CD74HC123NSRG4 数据手册

 浏览型号CD74HC123NSRG4的Datasheet PDF文件第2页浏览型号CD74HC123NSRG4的Datasheet PDF文件第3页浏览型号CD74HC123NSRG4的Datasheet PDF文件第4页浏览型号CD74HC123NSRG4的Datasheet PDF文件第5页浏览型号CD74HC123NSRG4的Datasheet PDF文件第6页浏览型号CD74HC123NSRG4的Datasheet PDF文件第7页 
CD54/74HC123, CD54/74HCT123,  
CD74HC423, CD74HCT423  
Data sheet acquired from Harris Semiconductor  
SCHS142F  
High-Speed CMOS Logic Dual Retriggerable  
Monostable Multivibrators with Resets  
September 1997 - Revised October 2003  
Features  
Ordering Information  
• Overriding Reset Terminates Output Pulse  
• Triggering From the Leading or Trailing Edge  
• Q and Q Buffered Outputs  
o
PART NUMBER  
CD54HC123F3A  
CD54HCT123F3A  
CD74HC123E  
TEMP. RANGE ( C)  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
[ /Title  
(CD74  
HC123  
,
CD74  
HCT12  
3,  
CD74  
HC423  
,
CD74  
HCT42  
3)  
• Separate Resets  
• Wide Range of Output-Pulse Widths  
• Schmitt Trigger on Both A and B Inputs  
• Fanout (Over Temperature Range)  
CD74HC123M  
CD74HC123MT  
CD74HC123M96  
CD74HC123NSR  
CD74HC123PW  
CD74HC123PWR  
CD74HC123PWT  
CD74HC423E  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
- 2V to 6V Operation  
CD74HC423M  
- High Noise Immunity: N = 30%, N = 30%of V  
IL IH  
at  
/Sub-  
ject  
(High  
Speed  
CC  
CD74HC423MT  
CD74HC423M96  
CD74HC423NSR  
CD74HCT123E  
CD74HCT123M  
CD74HCT123MT  
CD74HCT123M96  
CD74HCT423E  
CD74HCT423MT  
CD74HCT423M96  
V
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
Description  
The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are  
dual monostable multivibrators with resets. They are all  
retriggerable and differ only in that the 123 types can be  
triggered by a negative to positive reset pulse; whereas the  
423 types do not have this feature. An external resistor (R )  
X
and an external capacitor (C ) control the timing and the  
X
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
accuracy for the circuit. Adjustment of Rx and C provides a  
X
wide range of output pulse widths from the Q and Q  
terminals. Pulse triggering on the A and B inputs occur at a  
particular voltage level and is not related to the rise and fall  
times of the trigger pulses.  
Once triggered, the output pulse width may be extended by  
retriggering inputs A and B. The output pulse can be  
terminated by a LOW level on the Reset (R) pin. Trailing  
edge triggering (A) and leading edge triggering (B) inputs  
are provided for triggering from either edge of the input  
pulse. If either Mono is not used each input on the unused  
device (A, B, and R) must be terminated high or low.  
The minimum value of external resistance, Rx is typically  
5k. The minimum value external capacitance, CX, is 0pF.  
The calculation for the pulse width is t = 0.45 R C at  
W
X X  
V
= 5V.  
CC  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

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