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CD74HC08MM96EP PDF预览

CD74HC08MM96EP

更新时间: 2024-11-20 12:56:39
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
9页 309K
描述
QUADRUPLE 2-INPUT POSITIVE-AND GATES

CD74HC08MM96EP 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SOIC-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.09Is Samacsys:N
系列:HC/UHJESD-30 代码:R-PDSO-G14
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:27 ns传播延迟(tpd):135 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

CD74HC08MM96EP 数据手册

 浏览型号CD74HC08MM96EP的Datasheet PDF文件第2页浏览型号CD74HC08MM96EP的Datasheet PDF文件第3页浏览型号CD74HC08MM96EP的Datasheet PDF文件第4页浏览型号CD74HC08MM96EP的Datasheet PDF文件第5页浏览型号CD74HC08MM96EP的Datasheet PDF文件第6页浏览型号CD74HC08MM96EP的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢀ ꢅꢆ ꢇꢈ ꢉ  
ꢊ ꢋꢌꢁꢍ ꢋꢉꢎ ꢈ ꢏ ꢇꢐꢑ ꢉꢋꢒ ꢉꢓ ꢔꢐ ꢒ ꢐꢕꢈ ꢇꢌꢑ ꢁ ꢖ ꢌꢒꢈ ꢔ  
SCLS477B − APRIL 2003 − REVISED APRIL 2004  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
Balanced Propagation Delay and Transition  
Times  
Significant Power Reduction Compared to  
LSTTL Logic ICs  
D
D
D
D
D
D
Extended Temperature Performance of Up  
To −55°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
2-V to 6-V V  
Operation  
CC  
D
High Noise Immunity N or N = 30% of  
IL  
IH  
V
at V  
= 5 V  
CC  
CC  
Enhanced Product-Change Notification  
D
CMOS Input Compatibility, I 1 µA at V  
OH  
,
l
OL  
Qualification Pedigree  
V
Buffered Inputs  
M PACKAGE  
(TOP VIEW)  
Typical Propagation Delay 7 ns  
at V  
= 5 V, C = 15 pF, T = 25°C  
CC  
L A  
D
Fanout (Over Temperature Range)  
− Standard Outputs . . . 10 LSTTL Loads  
− Bus Driver Outputs . . . 15 LSTTL Loads  
1A  
1B  
V
CC  
13 4B  
1
2
3
4
5
6
7
14  
12  
11  
10  
9
1Y  
4A  
4Y  
3B  
3A  
3Y  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
2A  
2B  
2Y  
8
GND  
description/ordering information  
The CD74HC08 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL  
gates, with the low power consumption of standard CMOS integrated circuits. All devices can drive 10 LSTTL  
loads.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
−40°C to 125°C  
−55°C to 125°C  
SOIC − M  
SOIC − M  
Tape and reel  
Tape and reel  
CD74HC08QM96EP  
CD74HC08MM96EP  
HC08QEP  
HC08MEP  
§
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Product Preview  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
H
L
L
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢒꢢ  
Copyright 2004, Texas Instruments Incorporated  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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