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CD74FCT821AM PDF预览

CD74FCT821AM

更新时间: 2024-09-15 22:54:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
7页 43K
描述
BiCMOS FCT Interface Logic, 10- Bit D-Type Flip-Flops, Three-State

CD74FCT821AM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.72
系列:FCTJESD-30 代码:R-PDSO-G24
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:71400000 Hz
最大I(ol):0.048 A位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

CD74FCT821AM 数据手册

 浏览型号CD74FCT821AM的Datasheet PDF文件第2页浏览型号CD74FCT821AM的Datasheet PDF文件第3页浏览型号CD74FCT821AM的Datasheet PDF文件第4页浏览型号CD74FCT821AM的Datasheet PDF文件第5页浏览型号CD74FCT821AM的Datasheet PDF文件第6页浏览型号CD74FCT821AM的Datasheet PDF文件第7页 
CD74FCT821A,  
CD74FCT822A  
Data sheet acquired from Harris Semiconductor  
SCHS264  
BiCMOS FCT Interface Logic,  
January 1997  
10- Bit D-Type Flip-Flops, Three-State  
Features  
Description  
• Buffered Inputs  
The CD74FCT821A and CD74FCT822A ten bit, D-Type,  
three-state, positive edge triggered flip-flops use a small  
geometry BiCMOS technology. The output stage is a combi-  
nation of bipolar and CMOS transistors that limits the output  
• Typical Propagation Delay: 7.5ns at V  
o
= 5V,  
CC  
T = 25 C, C = 50pF  
A
L
HIGH level to two diode drops below V . This resultant  
lowering of output swing (0V to 3.7V) reduces power bus  
• CD74FCT821A  
- Noninverting  
CC  
ringing (a source of EMI) and minimizes V  
bounce and  
CC  
• CD74FCT822A  
- Inverting  
ground bounce and their effects during simultaneous output  
switching. The output configuration also enhances switching  
speed and is capable of sinking 48 milliamperes.  
• SCR Latchup Resistant BiCMOS Process and  
Circuit Design  
The ten flip-flops enter data into their registers on the LOW  
to HIGH transition of the clock(CP). The Output Enable (OE)  
controls the three state outputs and is independent of the  
register operation. When the Output Enable (OE) is HIGH,  
the outputs are in the high impedance state. The  
CD74FCT821A and CD74FCT822A share the same config-  
urations, but the CD74FCT821A outputs are noninverted  
while the CD74FCT822A devices have inverted outputs.  
• Speed of Bipolar FAST™/AS/S  
• 48mA Output Sink Current  
• Output Voltage Swing Limited to 3.7V at V  
• Controlled Output Edge Rates  
= 5V  
CC  
• Input/Output Isolation to V  
CC  
• BiCMOS Technology with Low Quiescent Power  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
24 Ld PDIP  
24 Ld PDIP  
24 Ld SOIC  
CD74FCT821AEN  
CD74FCT822AEN  
CD74FCT821AM  
0 to 70  
0 to 70  
0 to 70  
E24.3  
E24.3  
M24.3  
NOTE: When ordering the suffix M packages, use the entire part  
number. Add the suffix 96 to obtain the variant in the tape and reel.  
Pinouts  
CD74FCT821A  
(PDIP, SOIC)  
TOP VIEW  
CD74FCT822A  
(PDIP, SOIC)  
TOP VIEW  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
24  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
1
2
3
4
5
6
7
8
9
24  
V
V
CC  
CC  
23 Q0  
22 Q1  
21 Q2  
20 Q3  
19 Q4  
18 Q5  
17 Q6  
16 Q7  
15 Q8  
14 Q9  
13 CP  
23 Q0  
22 Q1  
21 Q2  
20 Q3  
19 Q4  
18 Q5  
17 Q6  
16 Q7  
15 Q8  
14 Q9  
13 CP  
D8 10  
D9 11  
D8 10  
D9 11  
GND 12  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1997  
File Number 2390.2  
8-1  

CD74FCT821AM 替代型号

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CY74FCT821CTSOCT TI

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