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CD74FCT574SM

更新时间： 2024-02-03 01:46:47
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路光电二极管信息通信管理驱动
页数 文件大小 规格书
5页 31K
描述
BiCMOS FCT Interface Logic, Octal D-Type Flip-Flops, Three-State

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CD74FCT574SM 数据手册

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CD74FCT564,  
CD74FCT574  
Data sheet acquired from Harris Semiconductor  
SCHS259  
BiCMOS FCT Interface Logic,  
January 1997  
Octal D-Type Flip-Flops, Three-State  
Features  
Description  
• Buffered Inputs  
The CD74FCT564 and CD74FCT574 are octal D-Type,  
three-state, positive edge triggered flip-flops which use a  
small geometry BiCMOS technology. The output stage is a  
combination of bipolar and CMOS transistors that limits the  
• Typical Propagation Delay: 5.6ns at V  
o
= 5V,  
CC  
T = 25 C  
A
output HIGH level to two diode drops below V . This result-  
ant lowering of output swing (0V to 3.7V) reduces power bus  
• Positive Edge Triggered  
CC  
• CD74FCT564  
- Inverting  
ringing (a source of EMI) and minimizes V  
bounce and  
CC  
ground bounce and their effects during simultaneous output  
switching. The output configuration also enhances switching  
speed and is capable of sinking 48 milliamperes.  
• CD74FCT574  
- Noninverting  
The eight flip-flops enter data into their registers on the LOW  
to HIGH transition of the clock (CP). The Output Enable (OE)  
controls the three state outputs and is independent of the  
register operation. When the Output Enable (OE) is HIGH,  
the outputs are in the high impedance state. The  
CD74FCT564 and CD74FCT574 share the same configura-  
tions; the CD74FCT564, however, has inverted outputs and  
the CD74FCT574 has noninverted outputs.  
• SCR Latchup Resistant BiCMOS Process and  
Circuit Design  
• Speed of Bipolar FAST™/AS/S  
• 48mA Output Sink Current  
• Output Voltage Swing Limited to 3.7V at V  
• Controlled Output Edge Rates  
= 5V  
CC  
• Input/Output Isolation to V  
CC  
Ordering Information  
• BiCMOS Technology with Low Quiescent Power  
TEMP.  
RANGE ( C)  
PKG.  
NO.  
o
PART NUMBER  
CD74FCT564E  
CD74FCT574E  
CD74FCT564M  
CD74FCT574M  
CD74FCT574SM  
PACKAGE  
20 Ld PDIP  
20 Ld PDIP  
20 Ld SOIC  
20 Ld SOIC  
20 Ld SSOP  
0 to 70  
E20.3  
0 to 70  
E20.3  
0 to 70  
M20.3  
M20.3  
M20.209  
0 to 70  
0 to 70  
NOTE: When ordering the suffix M and SM packages, use the entire  
part number. Add the suffix 96 to obtain the variant in the tape and reel.  
Pinouts  
CD74FCT564  
(PDIP, SOIC, SSOP)  
TOP VIEW  
CD74FCT574  
(PDIP, SOIC, SSOP)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
V
1
2
3
4
5
6
7
8
9
V
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
19  
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
19  
CC  
CC  
Q0  
Q0  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
12  
12  
Q7  
Q7  
GND 10  
11 CP  
GND 10  
11 CP  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1997  
File Number 2295.2  
8-1  
12345

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