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CD74FCT573 PDF预览

CD74FCT573

更新时间: 2024-02-04 10:48:45
品牌 Logo 应用领域
德州仪器 - TI 锁存器
页数 文件大小 规格书
7页 40K
描述
BiCMOS FCT Interface Logic, Octal Transparent Latches, Three-State

CD74FCT573 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:SSOP, SSOP20,.25Reach Compliance Code:unknown
风险等级:5.65Is Samacsys:N
其他特性:BROADSIDE VERSION OF 373系列:FCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):12 ns
认证状态:Not Qualified子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

CD74FCT573 数据手册

 浏览型号CD74FCT573的Datasheet PDF文件第2页浏览型号CD74FCT573的Datasheet PDF文件第3页浏览型号CD74FCT573的Datasheet PDF文件第4页浏览型号CD74FCT573的Datasheet PDF文件第5页浏览型号CD74FCT573的Datasheet PDF文件第6页浏览型号CD74FCT573的Datasheet PDF文件第7页 
CD74FCT573AT was not acquired from Harris Semiconductor.  
CD74FCT573,  
CD74FCT573AT  
Data sheet acquired from Harris Semiconductor  
SCHS260A  
BiCMOS FCT Interface Logic,  
January 1997  
Octal Transparent Latches, Three-State  
Features  
Description  
• Buffered Inputs  
The CD74FCT573 and CD74FCT573AT octal transparent  
latches use a small geometry BiCMOS technology. The out-  
put stage is a combination of bipolar and CMOS transistors  
that limits the output HIGH level to two diode drops below  
• Typical Propagation Delay: 3.9ns at V  
o
= 5V,  
CC  
T = 25 C, C = 50pF (CD74FCT573AT)  
A
L
• SCR Latchup Resistant BiCMOS Process and  
Circuit Design  
V
. This resultant lowering of output swing (0V to 3.7V)  
CC  
reduces power bus ringing (a source of EMI) and minimizes  
bounce and ground bounce and their effects during  
• FCTXXX Types  
V
CC  
- Speed of Bipolar FAST™/AS/S  
simultaneous output switching. The output configuration  
also enhances switching speed and is capable of sinking  
48 milliamperes.  
• FCTXXXAT Types  
- 30% Faster than FAST™/AS/S with Significantly  
Reduced Power Consumption  
The CD74FCT573 and CD74FCT573AT outputs are trans-  
parent to the inputs when the Latch Enable (LE) is HIGH.  
When the Latch Enable (LE) goes LOW, the data is latched.  
The Output Enable (OE) controls the three-state outputs.  
When the Output Enable (OE) is HIGH, the outputs are in  
the high impedance state. The latch operation is indepen-  
dent of the state of the Output Enable.  
• 48mA Output Sink Current  
• Output Voltage Swing Limited to 3.7V at V  
• Controlled Output Edge Rates  
= 5V  
CC  
• Input/Output Isolation to V  
CC  
• BiCMOS Technology with Low Quiescent Power  
Ordering Information  
TEMP.  
RANGE ( C)  
PKG.  
NO.  
o
PART NUMBER  
CD74FCT573ATE  
CD74FCT573M  
PACKAGE  
20 Ld PDIP  
20 Ld SOIC  
0 to 70  
E20.3  
M20.3  
0 to 70  
CD74FCT573SM  
0 to 70  
20 Ld SSOP M20.209  
NOTE: When ordering the suffix M and SM packages, use the entire  
part number. Add the suffix 96 to obtain the variant in the tape and reel.  
Pinout  
CD74FCT573, CD74FCT573AT  
(PDIP, SOIC, SSOP)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
V
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
19  
CC  
Q0  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
12  
Q7  
GND 10  
11 LE  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
FAST™ is a trademark of Fairchild Semiconductor.  
Copyright © Harris Corporation 1997  
File Number 2304.2  
8-1  

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