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CD74ACT161

更新时间: 2024-11-04 23:00:39
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德州仪器 - TI 计数器
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描述
4-BIT SYNCHRONOUS BINARY COUNTERS

CD74ACT161 数据手册

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CD54ACT161, CD74ACT161  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCHS298 – APRIL 2000  
CD54ACT161 . . . F PACKAGE  
CD74ACT161 . . . E OR M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Q
A
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
B
Q
B
C
Q
C
Exceeds 2 kV ESD Protection per  
MIL-STD-883, Method 3015  
D
Q
D
ENP  
GND  
ENT  
LOAD  
Package Options Include Plastic  
Small-Outline (M) Standard Plastic (E) and  
Ceramic (F) DIPs  
description  
The CD54ACT161 and CD74ACT161 devices are 4-bit binary counters. These synchronous, presettable  
counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous  
operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with  
each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of  
operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock)  
counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock  
waveform.  
These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.  
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes  
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low,  
regardless of the levels of the CLK, load (LOAD), or enable inputs.  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The CD54ACT161 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The CD74ACT161 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CD74ACT161 替代型号

型号 品牌 替代类型 描述 数据表
CD54ACT161 TI

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