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CD74ACT02EE4 PDF预览

CD74ACT02EE4

更新时间: 2024-11-18 05:09:07
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
9页 302K
描述
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

CD74ACT02EE4 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:DIP包装说明:ROHS COMPLIANT, PLASTIC, DIP-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.37Is Samacsys:N
系列:ACTJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.3 mm
负载电容(CL):50 pF逻辑集成电路类型:NOR GATE
最大I(ol):0.024 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:12.2 ns
传播延迟(tpd):12.2 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.35 mmBase Number Matches:1

CD74ACT02EE4 数据手册

 浏览型号CD74ACT02EE4的Datasheet PDF文件第2页浏览型号CD74ACT02EE4的Datasheet PDF文件第3页浏览型号CD74ACT02EE4的Datasheet PDF文件第4页浏览型号CD74ACT02EE4的Datasheet PDF文件第5页浏览型号CD74ACT02EE4的Datasheet PDF文件第6页浏览型号CD74ACT02EE4的Datasheet PDF文件第7页 
CD54ACT02, CD74ACT02  
QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
SCHS309B – JANUARY 2001 – REVISED MAY 2002  
CD54ACT02 . . . F PACKAGE  
CD74ACT02 . . . E OR M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1Y  
1A  
V
CC  
Balanced Propagation Delays  
1
2
3
4
5
6
7
14  
13  
12  
11  
4Y  
4B  
4A  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
1B  
2Y  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
2A  
10 3Y  
9
8
2B  
3B  
3A  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
GND  
description  
The ’ACT02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A  
or Y = A + B in positive logic.  
B
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74ACT02E  
CD74ACT02E  
CD74ACT02M  
CD74ACT02M96  
CD54ACT02F3A  
–55°C to 125°C  
SOIC – M  
ACT02M  
Tape and reel  
Tube  
CDIP – F  
CD54ACT02F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
L
L
H
logic diagram (positive logic)  
2
8
1A  
3
1
3A  
9
10  
13  
1Y  
2Y  
3Y  
4Y  
1B  
3B  
5
11  
4A  
2A  
6
4
12  
2B  
4B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CD74ACT02EE4 替代型号

型号 品牌 替代类型 描述 数据表
CD54ACT02F3A TI

完全替代

Quad 2-Input NOR Gate
CD74ACT02E TI

类似代替

Quad 2-Input NOR Gate
MC74ACT02NG ONSEMI

功能相似

Quad 2−Input NOR Gate

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