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CD74ACT00EE4 PDF预览

CD74ACT00EE4

更新时间: 2024-11-06 05:09:07
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
9页 301K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

CD74ACT00EE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.21Is Samacsys:N
系列:ACTJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.024 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:9.5 ns传播延迟(tpd):10.8 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD74ACT00EE4 数据手册

 浏览型号CD74ACT00EE4的Datasheet PDF文件第2页浏览型号CD74ACT00EE4的Datasheet PDF文件第3页浏览型号CD74ACT00EE4的Datasheet PDF文件第4页浏览型号CD74ACT00EE4的Datasheet PDF文件第5页浏览型号CD74ACT00EE4的Datasheet PDF文件第6页浏览型号CD74ACT00EE4的Datasheet PDF文件第7页 
CD54ACT00, CD74ACT00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCHS308B – JANUARY 2001 – REVISED JUNE 2002  
CD54ACT00 . . . F PACKAGE  
CD74ACT00 . . . E OR M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1A  
1B  
1Y  
2A  
2B  
V
CC  
Balanced Propagation Delays  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
2Y  
GND  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
8
description  
The ‘ACT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function  
of Y = A B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74ACT00E  
CD74ACT00E  
CD74ACT00M  
CD74ACT00M96  
CD54ACT00F3A  
–55°C to 125°C  
SOIC – M  
CDIP – F  
ACT00M  
Tape and reel  
Tube  
CD54ACT00F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CD74ACT00EE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT00NE4 TI

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QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN74ACT00N TI

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QUADRUPLE 2-INPUT POSITIVE-NAND GATES
CD74ACT00E TI

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Quad 2-Input NAND Gate

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