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CD74AC112ME4 PDF预览

CD74AC112ME4

更新时间： 2024-01-15 01:50:34
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 336K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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中文翻译

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CD74AC112ME4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, MS-012AC, SOIC-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.34Is Samacsys：N
系列：ACJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF逻辑集成电路类型：J-K FLIP-FLOP
最大频率@ Nom-Sup：71000000 Hz最大I（ol）：0.012 A
湿度敏感等级：1位数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3/5 V传播延迟（tpd）：129 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.5 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：3.9 mm
最小 fmax：100 MHzBase Number Matches：1

CD74AC112ME4 数据手册

 浏览型号CD74AC112ME4的Datasheet PDF文件第2页浏览型号CD74AC112ME4的Datasheet PDF文件第3页浏览型号CD74AC112ME4的Datasheet PDF文件第4页浏览型号CD74AC112ME4的Datasheet PDF文件第5页浏览型号CD74AC112ME4的Datasheet PDF文件第6页浏览型号CD74AC112ME4的Datasheet PDF文件第7页 
CD54AC112, CD74AC112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS325 – JANUARY 2003  
CD54AC112 . . . F PACKAGE  
CD74AC112 . . . E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1CLR  
2CLR  
2CLK  
2K  
1J  
Balanced Propagation Delays  
1PRE  
1Q  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
1Q  
11 2J  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
10  
9
2Q  
2PRE  
2Q  
GND  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description/ordering information  
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset  
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE  
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to  
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and  
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs  
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle  
flip-flops by tying J and K high.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
SOIC – M  
CDIP – F  
Tube  
Tube  
CD74AC112E  
CD74AC112M  
CD74AC112E  
–55°C to 125°C  
AC112M  
Tape and reel CD74AC112M96  
Tube CD54AC112F3A  
CD54AC112F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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