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CD74AC00M96G4 PDF预览

CD74AC00M96G4

更新时间: 2024-11-21 14:37:43
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 874K
描述
NAND Gate, AC Series, 4-Func, 2-Input, CMOS, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14

CD74AC00M96G4 技术参数

生命周期:Contact Manufacturer包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.67系列:AC
JESD-30 代码:R-PDSO-G14长度:8.65 mm
逻辑集成电路类型:NAND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):91 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

CD74AC00M96G4 数据手册

 浏览型号CD74AC00M96G4的Datasheet PDF文件第2页浏览型号CD74AC00M96G4的Datasheet PDF文件第3页浏览型号CD74AC00M96G4的Datasheet PDF文件第4页浏览型号CD74AC00M96G4的Datasheet PDF文件第5页浏览型号CD74AC00M96G4的Datasheet PDF文件第6页浏览型号CD74AC00M96G4的Datasheet PDF文件第7页 
CD54AC00, CD74AC00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCHS303C – JANUARY 2001 – REVISED JUNE 2002  
CD54AC00 . . . F PACKAGE  
CD74AC00 . . . E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply Voltage  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
2Y  
GND  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
8
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description  
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function  
of Y = A B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74AC00E  
CD74AC00E  
CD74AC00M  
CD74AC00M96  
CD54AC00F3A  
–55°C to 125°C  
SOIC – M  
CDIP – F  
AC00M  
Tape and reel  
Tube  
CD54AC00F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB  
design guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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