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SCLS455C − FEBRUARY 2001 − REVISED MAY 2004
CD54HCT573 . . . F PACKAGE
CD74HCT573 . . . DB, E, OR M PACKAGE
(TOP VIEW)
D
D
4.5-V to 5.5-V V
Operation
CC
Wide Operating Temperature Range of
−55°C to 125°C
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
D
D
D
D
Balanced Propagation Delays and
Transition Times
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
Standard Outputs Drive Up To 10 LS-TTL
Loads
Significant Power Reduction Compared to
LS-TTL Logic ICs
Inputs Are TTL-Voltage Compatible
description/ordering information
GND
The ’HCT573 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
PDIP − E Tube
CD74HCT573E
CD74HCT573E
HK573
SSOP − DB Tape and reel
Tube
CD74HCT573DBR
CD74HCT573M
CD74HCT573M96
CD54HCT573F3A
−55°C to 125°C
SOIC − M
HCT573M
Tape and reel
CDIP − F
Tube
CD54HCT573F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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