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CD54HCT4075F3A PDF预览

CD54HCT4075F3A

更新时间: 2024-12-01 05:18:03
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路
页数 文件大小 规格书
15页 380K
描述
High Speed CMOS Logic Triple 3-Input OR Gate

CD54HCT4075F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.66
系列:HCTJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.0052 A
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:36 ns传播延迟(tpd):36 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.67 mm
Base Number Matches:1

CD54HCT4075F3A 数据手册

 浏览型号CD54HCT4075F3A的Datasheet PDF文件第2页浏览型号CD54HCT4075F3A的Datasheet PDF文件第3页浏览型号CD54HCT4075F3A的Datasheet PDF文件第4页浏览型号CD54HCT4075F3A的Datasheet PDF文件第5页浏览型号CD54HCT4075F3A的Datasheet PDF文件第6页浏览型号CD54HCT4075F3A的Datasheet PDF文件第7页 
CD54HC4075, CD74HC4075,  
CD54HCT4075, CD74HCT4075  
Data sheet acquired from Harris Semiconductor  
SCHS210G  
High-Speed CMOS Logic  
Triple 3-Input OR Gate  
August 1997 - Revised June 2006  
Features  
Description  
• Buffered Inputs  
The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate  
CMOS technology to achieve operating speeds similar to  
LSTTL gates with the low power consumption of standard  
CMOS integrated circuits. All devices have the ability to drive  
10 LSTTL loads. The HCT logic family is functionally pin  
compatible with the standard LS logic family.  
• Typical Propagation Delay: 8ns at V  
o
= 5V,  
[ /Title  
(CD74H  
C4075,  
CD74H  
CT4075)  
/Subject  
(High  
Speed  
CMOS  
Logic  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC4075F3A  
CD54HC4075FK  
CD54HCT4075F3A  
CD74HC4075E  
( C)  
PACKAGE  
14 Ld CERDIP  
20 LCCC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
Triple 3-  
Input  
- 2V to 6V Operation  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
CD74HC4075M  
• HCT Types  
- 4.5V to 5.5V Operation  
CD74HC4075MT  
CD74HC4075M96  
CD74HC4075NSR  
CD74HC4075PW  
CD74HC4075PWR  
CD74HC4075PWT  
CD74HCT4075E  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2006, Texas Instruments Incorporated  
1

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