CD54/74HC374, CD54/74HCT374,
CD54/74HC574, CD54/74HCT574
Data sheet acquired from Harris Semiconductor
SCHS183C
High-Speed CMOS Logic Octal D-Type Flip-Flop,
3-State Positive-Edge Triggered
February 1998 - Revised May 2004
Features
Description
• Buffered Inputs
The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type
flip-flops with 3-state outputs and the capability to drive 15
• Common Three-State Output Enable Control
• Three-State Outputs
[ /Title
(CD74
HC374
,
LSTTL loads. The eight edge-triggered flip-flops enter data into
their registers on the LOW to HIGH transition of clock (CP). The
output enable (OE) controls the 3-state outputs and is
independent of the register operation. When OE is HIGH, the
outputs are in the high-impedance state. The 374 and 574 are
identical in function and differ only in their pinout arrangements.
• Bus Line Driving Capability
• Typical Propagation Delay (Clock to Q) = 15ns at
o
CD74
HCT37
4,
CD74
HC574
,
V
= 5V, C = 15pF, T = 25 C
L A
CC
• Fanout (Over Temperature Range)
Ordering Information
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
TEMP. RANGE
o
PART NUMBER
CD54HC374F3A
CD54HC574F3A
CD54HCT374F3A
CD54HCT574F3A
CD74HC374E
( C)
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
CD74
HCT57
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
CD74HC374M
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
- 2-V to 6-V Operation
CD74HC374M96
CD74HC574E
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC574M
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
• HCT Types
CD74HC574M96
CD74HCT374E
CD74HCT374M
CD74HCT374M96
CD74HCT574E
CD74HCT574M
CD74HCT574M96
CD74HCT574PWR
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
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