5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> CD54HC373F3A
CD54HC373F3A PDF预览

CD54HC373F3A

更新时间： 2024-11-25 22:00:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件
页数 文件大小 规格书
9页 310K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

CD54HC373F3A 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.38Is Samacsys：N
控制类型：ENABLE LOW/HIGH计数方向：UNIDIRECTIONAL
系列：HC/UHJESD-30 代码：R-GDIP-T20
长度：24.2 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.0078 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：45 ns
传播延迟（tpd）：265 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：FF/Latches
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：6.92 mm
Base Number Matches：1

CD54HC373F3A 数据手册

 浏览型号CD54HC373F3A的Datasheet PDF文件第2页浏览型号CD54HC373F3A的Datasheet PDF文件第3页浏览型号CD54HC373F3A的Datasheet PDF文件第4页浏览型号CD54HC373F3A的Datasheet PDF文件第5页浏览型号CD54HC373F3A的Datasheet PDF文件第6页浏览型号CD54HC373F3A的Datasheet PDF文件第7页 
CD54HC373, CD74HC373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003  
CD54HC373 . . . F PACKAGE  
CD74HC373 . . . E OR M PACKAGE  
(TOP VIEW)  
2-V to 6-V V  
Operation  
CC  
Wide Operating Temperature Range of  
–55°C to 125°C  
Balanced Propagation Delays and  
Transition Times  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
Standard Outputs Drive up to 15 LS-TTL  
Loads  
Significant Power Reduction Compared to  
LS-TTL Logic ICs  
description/ordering information  
The ’HC373 devices are octal transparent D-type  
GND  
latches designed for 2-V to 6-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs  
are latched at the logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74HC373E  
CD74HC373E  
CD74HC373M  
CD74HC373M96  
CD54HC373F3A  
–55°C to 125°C  
SOIC – M  
HC373M  
Tape and reel  
Tube  
CDIP – F  
CD54HC373F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

CD54HC373F3A 替代型号

型号 品牌 替代类型 描述 数据表
CD54HC373F TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SNJ54HC373J TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES
SN54HC373J TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与CD54HC373F3A相关器件

型号 品牌 获取价格 描述 数据表
CD54HC373FB RENESAS

获取价格

 		CD54HC373FB
CD54HC373H/3A RENESAS

获取价格

 		HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, UUC20
CD54HC373M ETC

获取价格

 		Logic IC
CD54HC374 TI

获取价格

 		High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered
CD54HC374_03 TI

获取价格

 		High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered
CD54HC374_07 TI

获取价格

 		High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered
CD54HC374_16 TI

获取价格

 		High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered
CD54HC374E ETC

获取价格

 		Logic IC
CD54HC374EN ETC

获取价格

 		Logic IC
CD54HC374F ETC

获取价格

 		Logic IC

与CD54HC373F3A相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证