CD54HC32, CD74HC32,
CD54HCT32, CD74HCT32
Data sheet acquired from Harris Semiconductor
SCHS274C
High-Speed CMOS Logic
Quad 2-Input OR Gate
September 1997 - Revised September 2003
Features
Description
• Typical Propagation Delay: 7ns at V
CC
= 5V,
The ’HC32 and ’HCT32 contain four 2-input OR gates in one
package. Logic gates utilize silicon gate CMOS technology
to achieve operating speeds similar to LSTTL gates with the
low power consumption of standard CMOS integrated cir-
cuits. All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the
standard LS logic family.
o
C = 15pF, T = 25 C
L
A
[ /Title
(CD54
HCT32
,
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
CD74
HC32,
CD74
HCT32
)
/Sub-
ject
(High
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
TEMP. RANGE
o
PART NUMBER
CD54HC32F3A
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
• HC Types
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- 2V to 6V Operation
CD54HCT32F3A
CD74HC32E
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
• HCT Types
CD74HC32M
- 4.5V to 5.5V Operation
CD74HC32MT
CD74HC32M96
CD74HCT32E
CD74HCT32M
CD74HCT32MT
CD74HCT32M96
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC32, CD54HCT32
(CERDIP)
CD74HC32, CD74HCT32
(PDIP, SOIC)
TOP VIEW
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
1Y
2A
2B
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated.
1