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CD54FCT373ATM PDF预览

CD54FCT373ATM

更新时间： 2024-11-08 00:00:55
品牌 Logo 应用领域
德州仪器 - TI 锁存器逻辑集成电路光电二极管信息通信管理驱动
页数 文件大小 规格书
3页 24K
描述
FCT Interface Logic Octal Transparent Latch, Three-State

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CD54FCT373ATM 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.73系列：FCT
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：2.65 mm标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mm

CD54FCT373ATM 数据手册

 浏览型号CD54FCT373ATM的Datasheet PDF文件第2页浏览型号CD54FCT373ATM的Datasheet PDF文件第3页 
CD54/74FCT373,  
CD54/74FCT373AT,  
Data sheet acquired from Harris Semiconductor  
SCHS272  
CD54/74FCT533  
FCT Interface Logic  
Octal Transparent Latch, Three-State  
February 1996  
Features  
Description  
• CD54/74FCT373, CD54/74FCT373AT - Non-Inverting  
The CD54/74FCT373, 373AT, and 533 octal transparent  
latches use a small-geometry BiCMOS technology. The output  
stage is a combination of bipolar and CMOS transistors that  
limits the output-HIGH level to two diode drops below VCC. This  
resultant lowering of output swing (0V to 3.7V) reduces power  
bus ringing (a source of EMI) and minimizes VCC bounce and  
ground bounce and their effects during simultaneous output  
switching. The output configuration also enhances switching  
speed and is capable of sinking 32mA to 48mA.  
• CD54/74FCT533 - Inverting  
• Buffered inputs  
• Typical Propagation Delay: 3.9ns at VCC = 5V,  
o
TA = +25 C, CL = 50pF (FCT373AT)  
• SCR-Latchup-Resistant BiCMOS Process and Circuit  
Design  
The CD54/74FCT373, 373AT, and 533 outputs are transpar-  
ent to the inputs when the Latch Enable (LE) is HIGH. When  
the Latch Enable (LE) goes LOW, the data is latched. The  
Output Enable (OE) controls the three-state outputs. When  
the Output Enable (OE) is HIGH, the outputs are in the high-  
impedance state. The latch operation is independent of the  
state of the Output Enable.  
• FCTXXX Types - Speed of Bipolar FAST®/AS/S;  
FCTXXXAT Types - 30% Faster than FAST/AS/S with  
Significantly Reduced Power Consumption  
• 48mA to 32mA Output Sink Current (Commercial/  
Extended Industrial)  
• Output Voltage Swing Limited to 3.7V at VCC = 5V  
• Controlled Output-Edge Rates  
Ordering Information  
o
PART NUMBER  
CD54/74FCT373E  
CD54/74FCT373ATE  
CD54/74FCT533E  
CD54/74FCT373M  
CD54/74FCT373ATM  
CD54/74FCT533M  
CD54/74FCT373SM  
CD54/74FCT533SM  
CD54FCT373H  
TEMP. RANGE ( C)  
PACKAGE  
• Input/Output Isolation to VCC  
-55 to 125, 0 to 70 20 Ld PDIP  
-55 to 125, 0 to 70 20 Ld PDIP  
-55 to 125, 0 to 70 20 Ld PDIP  
-55 to 125, 0 to 70 20 Ld SOIC  
-55 to 125, 0 to 70 20 Ld SOIC  
-55 to 125, 0 to 70 20 Ld SOIC  
-55 to 125, 0 to 70 20 Ld SSOP  
-55 to 125, 0 to 70 20 Ld SSOP  
-55 to 125  
• BiCMOS Technology with Low Quiescent Power  
CD54FCT533H  
-55 to 125  
Functional Diagram  
TRUTH TABLE  
373  
533  
OUTPUT  
ENABLE  
LATCH  
ENABLE  
373,373AT  
OUTPUT  
533  
OUTPUT  
3
4
2
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
DATA  
5
7
6
L
L
L
L
H
H
H
L
H
L
I
H
L
L
H
H
L
8
9
13  
14  
17  
18  
12  
15  
16  
19  
L
L
h
X
H
Z
X
Z
11  
1
LE  
H = HIGH voltage level.  
L = LOW voltage level.  
X = Irrelevant.  
I = LOW voltage level one setup time  
prior to the high-to-low latch enable  
transition.  
OE  
Z = HIGH Impedance.  
h = HIGH voltage level one setup time  
prior to the high-to-low latch enable  
transition.  
FAST® is a registered trademark of Fairchild Semiconductor Corporation.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 2230.2  
Copyright © Harris Corporation 1996  
1
123

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